1 /*- 2 * Copyright (c) 2017 The FreeBSD Foundation 3 * 4 * This software was developed by Landon Fuller under sponsorship from 5 * the FreeBSD Foundation. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer, 12 * without modification. 13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 14 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 15 * redistribution must be conditioned upon including a substantially 16 * similar Disclaimer requirement for further binary redistribution. 17 * 18 * NO WARRANTY 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 21 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 22 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 23 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 24 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 27 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 29 * THE POSSIBILITY OF SUCH DAMAGES. 30 * 31 * $FreeBSD$ 32 */ 33 34 #ifndef _MIPS_BROADCOM_BCM_MIPSVAR_H_ 35 #define _MIPS_BROADCOM_BCM_MIPSVAR_H_ 36 37 #include <sys/param.h> 38 #include <sys/bus.h> 39 #include <sys/intr.h> 40 #include <sys/lock.h> 41 42 #include <machine/intr.h> 43 44 DECLARE_CLASS(bcm_mips_driver); 45 46 struct bcm_mips_irqsrc; 47 struct bcm_mips_softc; 48 49 #define BCM_MIPS_NINTR 32 /**< maximum number of addressable backplane interrupt vectors */ 50 #define BCM_MIPS_IRQ_SHARED 0 /**< MIPS CPU IRQ reserved for shared interrupt handling */ 51 #define INTR_MAP_DATA_BCM_MIPS INTR_MAP_DATA_PLAT_2 /**< Broadcom MIPS PIC interrupt map data type */ 52 53 int bcm_mips_attach(device_t dev, u_int num_cpuirqs, u_int timer_irq, 54 driver_filter_t filter); 55 int bcm_mips_detach(device_t dev); 56 57 /** 58 * Broadcom MIPS PIC interrupt map data. 59 */ 60 struct bcm_mips_intr_map_data { 61 struct intr_map_data mdata; 62 u_int ivec; /**< bus interrupt vector */ 63 }; 64 65 /** 66 * Nested MIPS CPU interrupt handler state. 67 */ 68 struct bcm_mips_cpuirq { 69 struct bcm_mips_softc *sc; /**< driver instance state, or NULL if uninitialized. */ 70 u_int mips_irq; /**< mips hardware interrupt number (relative to NSOFT_IRQ) */ 71 int irq_rid; /**< mips IRQ resource id, or -1 if this entry is unavailable */ 72 struct resource *irq_res; /**< mips interrupt resource */ 73 void *irq_cookie; /**< mips interrupt handler cookie, or NULL */ 74 struct bcm_mips_irqsrc *isrc_solo; /**< solo isrc assigned to this interrupt, or NULL */ 75 u_int refs; /**< isrc consumer refcount */ 76 }; 77 78 /** 79 * Broadcom MIPS PIC interrupt source definition. 80 */ 81 struct bcm_mips_irqsrc { 82 struct intr_irqsrc isrc; 83 u_int ivec; /**< bus interrupt vector */ 84 u_int refs; /**< active reference count */ 85 struct bcm_mips_cpuirq *cpuirq; /**< assigned MIPS HW IRQ, or NULL if no assignment */ 86 }; 87 88 /** 89 * bcm_mips driver instance state. Must be first member of all subclass 90 * softc structures. 91 */ 92 struct bcm_mips_softc { 93 device_t dev; 94 struct bcm_mips_cpuirq cpuirqs[NREAL_IRQS]; /**< nested CPU IRQ handlers */ 95 u_int num_cpuirqs; /**< number of nested CPU IRQ handlers */ 96 u_int timer_irq; /**< CPU timer IRQ */ 97 struct bcm_mips_irqsrc isrcs[BCM_MIPS_NINTR]; 98 struct mtx mtx; 99 }; 100 101 #define BCM_MIPS_IVEC_MASK(_isrc) (1 << ((_isrc)->ivec)) 102 103 #define BCM_MIPS_LOCK_INIT(sc) \ 104 mtx_init(&(sc)->mtx, device_get_nameunit((sc)->dev), \ 105 "bhnd mips driver lock", MTX_DEF) 106 #define BCM_MIPS_LOCK(sc) mtx_lock(&(sc)->mtx) 107 #define BCM_MIPS_UNLOCK(sc) mtx_unlock(&(sc)->mtx) 108 #define BCM_MIPS_LOCK_ASSERT(sc, what) mtx_assert(&(sc)->mtx, what) 109 #define BCM_MIPS_LOCK_DESTROY(sc) mtx_destroy(&(sc)->mtx) 110 111 #endif /* _MIPS_BROADCOM_BCM_MIPSVAR_H_ */ 112