1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2018 Emmanuel Vadot <[email protected]>
5 * Copyright (c) 2018 Greg V <[email protected]>
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 *
28 * $FreeBSD$
29 */
30
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
33
34 #include <sys/param.h>
35 #include <sys/systm.h>
36 #include <sys/bus.h>
37 #include <sys/rman.h>
38 #include <sys/kernel.h>
39 #include <sys/module.h>
40 #include <machine/bus.h>
41
42 #include <dev/fdt/simplebus.h>
43
44 #include <dev/ofw/ofw_bus.h>
45 #include <dev/ofw/ofw_bus_subr.h>
46
47 #include <dev/extres/clk/clk_div.h>
48 #include <dev/extres/clk/clk_fixed.h>
49 #include <dev/extres/clk/clk_mux.h>
50
51 #include <arm64/rockchip/clk/rk_cru.h>
52
53 #include <arm64/rockchip/clk/rk3399_cru_dt.h>
54
55 #define CRU_CLKSEL_CON(x) (0x100 + (x) * 0x4)
56 #define CRU_CLKGATE_CON(x) (0x300 + (x) * 0x4)
57
58 /* GATES */
59
60 static struct rk_cru_gate rk3399_gates[] = {
61 /* CRU_CLKGATE_CON0 */
62 /* 15-8 unused */
63 GATE(SCLK_PVTM_CORE_L, "clk_pvtm_core_l", "xin24m", 0, 7),
64 GATE(0, "pclk_dbg_core_l", "pclk_dbg_core_l_c", 0, 6),
65 GATE(0, "atclk_core_l", "atclk_core_l_c", 0, 5),
66 GATE(0, "aclkm_core_l", "aclkm_core_l_c", 0, 4),
67 GATE(0, "clk_core_l_gpll_src", "gpll", 0, 3),
68 GATE(0, "clk_core_l_dpll_src", "dpll", 0, 2),
69 GATE(0, "clk_core_l_bpll_src", "bpll", 0, 1),
70 GATE(0, "clk_core_l_lpll_src", "lpll", 0, 0),
71
72 /* CRU_CLKGATE_CON1 */
73 /* 15 - 8 unused */
74 GATE(SCLK_PVTM_CORE_B, "clk_pvtm_core_b", "xin24m", 1, 7),
75 GATE(0, "pclk_dbg_core_b","pclk_dbg_core_b_c", 1, 6),
76 GATE(0, "atclk_core_b", "atclk_core_b_c", 1, 5),
77 GATE(0, "aclkm_core_b", "aclkm_core_b_c", 1, 4),
78 GATE(0, "clk_core_b_gpll_src", "gpll", 1, 3),
79 GATE(0, "clk_core_b_dpll_src", "dpll", 1, 2),
80 GATE(0, "clk_core_b_bpll_src", "bpll", 1, 1),
81 GATE(0, "clk_core_b_lpll_src", "lpll", 1, 0),
82
83 /* CRU_CLKGATE_CON2 */
84 /* 15 - 11 unused */
85 GATE(0, "npll_cs", "npll", 2, 10),
86 GATE(0, "gpll_cs", "gpll", 2, 9),
87 GATE(0, "cpll_cs", "cpll", 2, 8),
88 GATE(SCLK_CCI_TRACE, "clk_cci_trace", "clk_cci_trace_c", 2, 7),
89 GATE(0, "gpll_cci_trace", "gpll", 2, 6),
90 GATE(0, "cpll_cci_trace", "cpll", 2, 5),
91 GATE(0, "aclk_cci_pre", "aclk_cci_pre_c", 2, 4),
92 GATE(0, "vpll_aclk_cci_src", "vpll", 2, 3),
93 GATE(0, "npll_aclk_cci_src", "npll", 2, 2),
94 GATE(0, "gpll_aclk_cci_src", "gpll", 2, 1),
95 GATE(0, "cpll_aclk_cci_src", "cpll", 2, 0),
96
97 /* CRU_CLKGATE_CON3 */
98 /* 15 - 8 unused */
99 GATE(0, "aclk_center", "aclk_center_c", 3, 7),
100 /* 6 unused */
101 /* 5 unused */
102 GATE(PCLK_DDR, "pclk_ddr", "pclk_ddr_c", 3, 4),
103 GATE(0, "clk_ddrc_gpll_src", "gpll", 3, 3),
104 GATE(0, "clk_ddrc_dpll_src", "dpll", 3, 2),
105 GATE(0, "clk_ddrc_bpll_src", "bpll", 3, 1),
106 GATE(0, "clk_ddrc_lpll_src", "lpll", 3, 0),
107
108 /* CRU_CLKGATE_CON4 */
109 /* 15 - 12 unused */
110 GATE(SCLK_PVTM_DDR, "clk_pvtm_ddr", "xin24m", 4, 11),
111 GATE(0, "clk_rga_core", "clk_rga_core_c", 4, 10),
112 GATE(0, "hclk_rga_pre", "hclk_rga_pre_c", 4, 9),
113 GATE(0, "aclk_rga_pre", "aclk_rga_pre_c", 4, 8),
114 GATE(0, "hclk_iep_pre", "hclk_iep_pre_c", 4, 7),
115 GATE(0, "aclk_iep_pre", "aclk_iep_pre_c", 4, 6),
116 GATE(SCLK_VDU_CA, "clk_vdu_ca", "clk_vdu_ca_c", 4, 5),
117 GATE(SCLK_VDU_CORE, "clk_vdu_core", "clk_vdu_core_c", 4, 4),
118 GATE(0, "hclk_vdu_pre", "hclk_vdu_pre_c", 4, 3),
119 GATE(0, "aclk_vdu_pre", "aclk_vdu_pre_c", 4, 2),
120 GATE(0, "hclk_vcodec_pre", "hclk_vcodec_pre_c", 4, 1),
121 GATE(0, "aclk_vcodec_pre", "aclk_vcodec_pre_c", 4, 0),
122
123 /* CRU_CLKGATE_CON5 */
124 /* 15 - 10 unused */
125 GATE(SCLK_MAC_TX, "clk_rmii_tx", "clk_rmii_src", 5, 9),
126 GATE(SCLK_MAC_RX, "clk_rmii_rx", "clk_rmii_src", 5, 8),
127 GATE(SCLK_MACREF, "clk_mac_ref", "clk_rmii_src", 5, 7),
128 GATE(SCLK_MACREF_OUT, "clk_mac_refout", "clk_rmii_src", 5, 6),
129 GATE(SCLK_MAC, "clk_gmac", "clk_gmac_c", 5, 5),
130 GATE(PCLK_PERIHP, "pclk_perihp", "pclk_perihp_c", 5, 4),
131 GATE(HCLK_PERIHP, "hclk_perihp", "hclk_perihp_c", 5, 3),
132 GATE(ACLK_PERIHP, "aclk_perihp", "aclk_perihp_c", 5, 2),
133 GATE(0, "cpll_aclk_perihp_src", "cpll", 5, 1),
134 GATE(0, "gpll_aclk_perihp_src", "gpll", 5, 0),
135
136 /* CRU_CLKGATE_CON6 */
137 /* 15 unused */
138 GATE(SCLK_EMMC, "clk_emmc", "clk_emmc_c", 6, 14),
139 GATE(0, "cpll_aclk_emmc_src", "cpll", 6, 13),
140 GATE(0, "gpll_aclk_emmc_src", "gpll", 6, 12),
141 GATE(0, "pclk_gmac_pre", "pclk_gmac_pre_c", 6, 11),
142 GATE(0, "aclk_gmac_pre", "aclk_gmac_pre_c", 6, 10),
143 GATE(0, "cpll_aclk_gmac_src", "cpll", 6, 9),
144 GATE(0, "gpll_aclk_gmac_src", "gpll", 6, 8),
145 /* 7 unused */
146 GATE(SCLK_USB2PHY1_REF, "clk_usb2phy1_ref", "xin24m", 6, 6),
147 GATE(SCLK_USB2PHY0_REF, "clk_usb2phy0_ref", "xin24m", 6, 5),
148 GATE(SCLK_HSICPHY, "clk_hsicphy", "clk_hsicphy_c", 6, 4),
149 GATE(0, "clk_pcie_core_cru", "clk_pcie_core_cru_c", 6, 3),
150 GATE(SCLK_PCIE_PM, "clk_pcie_pm", "clk_pcie_pm_c", 6, 2),
151 GATE(SCLK_SDMMC, "clk_sdmmc", "clk_sdmmc_c", 6, 1),
152 GATE(SCLK_SDIO, "clk_sdio", "clk_sdio_c", 6, 0),
153
154 /* CRU_CLKGATE_CON7 */
155 /* 15 - 10 unused */
156 GATE(FCLK_CM0S, "fclk_cm0s", "fclk_cm0s_c", 7, 9),
157 GATE(SCLK_CRYPTO1, "clk_crypto1", "clk_crypto1_c", 7, 8),
158 GATE(SCLK_CRYPTO0, "clk_crypto0", "clk_crypto0_c", 7, 7),
159 GATE(0, "cpll_fclk_cm0s_src", "cpll", 7, 6),
160 GATE(0, "gpll_fclk_cm0s_src", "gpll", 7, 5),
161 GATE(PCLK_PERILP0, "pclk_perilp0", "pclk_perilp0_c", 7, 4),
162 GATE(HCLK_PERILP0, "hclk_perilp0", "hclk_perilp0_c", 7, 3),
163 GATE(ACLK_PERILP0, "aclk_perilp0", "aclk_perilp0_c", 7, 2),
164 GATE(0, "cpll_aclk_perilp0_src", "cpll", 7, 1),
165 GATE(0, "gpll_aclk_perilp0_src", "gpll", 7, 0),
166
167 /* CRU_CLKGATE_CON8 */
168 GATE(SCLK_SPDIF_8CH, "clk_spdif", "clk_spdif_mux", 8, 15),
169 GATE(0, "clk_spdif_frac", "clk_spdif_frac_c", 8, 14),
170 GATE(0, "clk_spdif_div", "clk_spdif_div_c", 8, 13),
171 GATE(SCLK_I2S_8CH_OUT, "clk_i2sout", "clk_i2sout_c", 8, 12),
172 GATE(SCLK_I2S2_8CH, "clk_i2s2", "clk_i2s2_mux", 8, 11),
173 GATE(0, "clk_i2s2_frac", "clk_i2s2_frac_c", 8, 10),
174 GATE(0, "clk_i2s2_div", "clk_i2s2_div_c", 8, 9),
175 GATE(SCLK_I2S1_8CH, "clk_i2s1", "clk_i2s1_mux", 8, 8),
176 GATE(0, "clk_i2s1_frac", "clk_i2s1_frac_c", 8, 7),
177 GATE(0, "clk_i2s1_div", "clk_i2s1_div_c", 8, 6),
178 GATE(SCLK_I2S0_8CH, "clk_i2s0", "clk_i2s0_mux", 8, 5),
179 GATE(0, "clk_i2s0_frac","clk_i2s0_frac_c", 8, 4),
180 GATE(0, "clk_i2s0_div","clk_i2s0_div_c", 8, 3),
181 GATE(PCLK_PERILP1, "pclk_perilp1", "pclk_perilp1_c", 8, 2),
182 GATE(HCLK_PERILP1, "cpll_hclk_perilp1_src", "cpll", 8, 1),
183 GATE(0, "gpll_hclk_perilp1_src", "gpll", 8, 0),
184
185 /* CRU_CLKGATE_CON9 */
186 GATE(SCLK_SPI4, "clk_spi4", "clk_spi4_c", 9, 15),
187 GATE(SCLK_SPI2, "clk_spi2", "clk_spi2_c", 9, 14),
188 GATE(SCLK_SPI1, "clk_spi1", "clk_spi1_c", 9, 13),
189 GATE(SCLK_SPI0, "clk_spi0", "clk_spi0_c", 9, 12),
190 GATE(SCLK_SARADC, "clk_saradc", "clk_saradc_c", 9, 11),
191 GATE(SCLK_TSADC, "clk_tsadc", "clk_tsadc_c", 9, 10),
192 /* 9 - 8 unused */
193 GATE(0, "clk_uart3_frac", "clk_uart3_frac_c", 9, 7),
194 GATE(0, "clk_uart3_div", "clk_uart3_div_c", 9, 6),
195 GATE(0, "clk_uart2_frac", "clk_uart2_frac_c", 9, 5),
196 GATE(0, "clk_uart2_div", "clk_uart2_div_c", 9, 4),
197 GATE(0, "clk_uart1_frac", "clk_uart1_frac_c", 9, 3),
198 GATE(0, "clk_uart1_div", "clk_uart1_div_c", 9, 2),
199 GATE(0, "clk_uart0_frac", "clk_uart0_frac_c", 9, 1),
200 GATE(0, "clk_uart0_div", "clk_uart0_div_c", 9, 0),
201
202 /* CRU_CLKGATE_CON10 */
203 GATE(SCLK_VOP1_PWM, "clk_vop1_pwm", "clk_vop1_pwm_c", 10, 15),
204 GATE(SCLK_VOP0_PWM, "clk_vop0_pwm", "clk_vop0_pwm_c", 10, 14),
205 GATE(DCLK_VOP0_DIV, "dclk_vop0_div", "dclk_vop0_div_c", 10, 12),
206 GATE(DCLK_VOP1_DIV, "dclk_vop1_div", "dclk_vop1_div_c", 10, 13),
207 GATE(0, "hclk_vop1_pre", "hclk_vop1_pre_c", 10, 11),
208 GATE(ACLK_VOP1_PRE, "aclk_vop1_pre", "aclk_vop1_pre_c", 10, 10),
209 GATE(0, "hclk_vop0_pre", "hclk_vop0_pre_c", 10, 9),
210 GATE(ACLK_VOP0_PRE, "aclk_vop0_pre", "aclk_vop0_pre_c", 10, 8),
211 GATE(0, "clk_cifout_src", "clk_cifout_src_c", 10, 7),
212 GATE(SCLK_SPDIF_REC_DPTX, "clk_spdif_rec_dptx", "clk_spdif_rec_dptx_c", 10, 6),
213 GATE(SCLK_I2C7, "clk_i2c7", "clk_i2c7_c", 10, 5),
214 GATE(SCLK_I2C3, "clk_i2c3", "clk_i2c3_c", 10, 4),
215 GATE(SCLK_I2C6, "clk_i2c6", "clk_i2c6_c", 10, 3),
216 GATE(SCLK_I2C2, "clk_i2c2", "clk_i2c2_c", 10, 2),
217 GATE(SCLK_I2C5, "clk_i2c5", "clk_i2c5_c", 10, 1),
218 GATE(SCLK_I2C1, "clk_i2c1", "clk_i2c1_c", 10, 0),
219
220 /* CRU_CLKGATE_CON11 */
221 GATE(SCLK_MIPIDPHY_CFG, "clk_mipidphy_cfg", "xin24m", 11, 15),
222 GATE(SCLK_MIPIDPHY_REF, "clk_mipidphy_ref", "xin24m", 11, 14),
223 /* 13-12 unused */
224 GATE(PCLK_EDP, "pclk_edp", "pclk_edp_c", 11, 11),
225 GATE(PCLK_HDCP, "pclk_hdcp", "pclk_hdcp_c", 11, 10),
226 /* 9 unuwsed */
227 GATE(SCLK_DP_CORE, "clk_dp_core", "clk_dp_core_c", 11, 8),
228 GATE(SCLK_HDMI_CEC, "clk_hdmi_cec", "clk_hdmi_cec_c", 11, 7),
229 GATE(SCLK_HDMI_SFR, "clk_hdmi_sfr", "xin24m", 11, 6),
230 GATE(SCLK_ISP1, "clk_isp1", "clk_isp1_c", 11, 5),
231 GATE(SCLK_ISP0, "clk_isp0", "clk_isp0_c", 11, 4),
232 GATE(HCLK_HDCP, "hclk_hdcp", "hclk_hdcp_c", 11, 3),
233 GATE(ACLK_HDCP, "aclk_hdcp", "aclk_hdcp_c", 11, 2),
234 GATE(PCLK_VIO, "pclk_vio", "pclk_vio_c", 11, 1),
235 GATE(ACLK_VIO, "aclk_vio", "aclk_vio_c", 11, 0),
236
237 /* CRU_CLKGATE_CON12 */
238 /* 15 - 14 unused */
239 GATE(HCLK_SD, "hclk_sd", "hclk_sd_c", 12, 13),
240 GATE(ACLK_GIC_PRE, "aclk_gic_pre", "aclk_gic_pre_c", 12, 12),
241 GATE(HCLK_ISP1, "hclk_isp1", "hclk_isp1_c", 12, 11),
242 GATE(ACLK_ISP1, "aclk_isp1", "aclk_isp1_c", 12, 10),
243 GATE(HCLK_ISP0, "hclk_isp0", "hclk_isp0_c", 12, 9),
244 GATE(ACLK_ISP0, "aclk_isp0", "aclk_isp0_c", 12, 8),
245 /* 7 unused */
246 GATE(SCLK_PCIEPHY_REF100M, "clk_pciephy_ref100m", "clk_pciephy_ref100m_c", 12, 6),
247 /* 5 unused */
248 GATE(SCLK_USB3OTG1_SUSPEND, "clk_usb3otg1_suspend", "clk_usb3otg1_suspend_c", 12, 4),
249 GATE(SCLK_USB3OTG0_SUSPEND, "clk_usb3otg0_suspend", "clk_usb3otg0_suspend_c", 12, 3),
250 GATE(SCLK_USB3OTG1_REF, "clk_usb3otg1_ref", "xin24m", 12, 2),
251 GATE(SCLK_USB3OTG0_REF, "clk_usb3otg0_ref", "xin24m", 12, 1),
252 GATE(ACLK_USB3, "aclk_usb3", "aclk_usb3_c", 12, 0),
253
254 /* CRU_CLKGATE_CON13 */
255 GATE(SCLK_TESTCLKOUT2, "clk_testout2", "clk_testout2_c", 13, 15),
256 GATE(SCLK_TESTCLKOUT1, "clk_testout1", "clk_testout1_c", 13, 14),
257 GATE(SCLK_SPI5, "clk_spi5", "clk_spi5_c", 13, 13),
258 GATE(0, "clk_usbphy0_480m_src", "clk_usbphy0_480m", 13, 12),
259 GATE(0, "clk_usbphy1_480m_src", "clk_usbphy1_480m", 13, 12),
260 GATE(0, "clk_test", "clk_test_c", 13, 11),
261 /* 10 unused */
262 GATE(0, "clk_test_frac", "clk_test_frac_c", 13, 9),
263 /* 8 unused */
264 GATE(SCLK_UPHY1_TCPDCORE, "clk_uphy1_tcpdcore", "clk_uphy1_tcpdcore_c", 13, 7),
265 GATE(SCLK_UPHY1_TCPDPHY_REF, "clk_uphy1_tcpdphy_ref", "clk_uphy1_tcpdphy_ref_c", 13, 6),
266 GATE(SCLK_UPHY0_TCPDCORE, "clk_uphy0_tcpdcore", "clk_uphy0_tcpdcore_c", 13, 5),
267 GATE(SCLK_UPHY0_TCPDPHY_REF, "clk_uphy0_tcpdphy_ref", "clk_uphy0_tcpdphy_ref_c", 13, 4),
268 /* 3 - 2 unused */
269 GATE(SCLK_PVTM_GPU, "aclk_pvtm_gpu", "xin24m", 13, 1),
270 GATE(0, "aclk_gpu_pre", "aclk_gpu_pre_c", 13, 0),
271
272 /* CRU_CLKGATE_CON14 */
273 /* 15 - 14 unused */
274 GATE(ACLK_PERF_CORE_L, "aclk_perf_core_l", "aclkm_core_l", 14, 13),
275 GATE(ACLK_CORE_ADB400_CORE_L_2_CCI500, "aclk_core_adb400_core_l_2_cci500", "aclkm_core_l", 14, 12),
276 GATE(ACLK_GIC_ADB400_CORE_L_2_GIC, "aclk_core_adb400_core_l_2_gic", "armclkl", 14, 11),
277 GATE(ACLK_GIC_ADB400_GIC_2_CORE_L, "aclk_core_adb400_gic_2_core_l", "armclkl", 14, 10),
278 GATE(0, "clk_dbg_pd_core_l", "armclkl", 14, 9),
279 /* 8 - 7 unused */
280 GATE(ACLK_PERF_CORE_B, "aclk_perf_core_b", "aclkm_core_b", 14, 6),
281 GATE(ACLK_CORE_ADB400_CORE_B_2_CCI500, "aclk_core_adb400_core_b_2_cci500", "aclkm_core_b", 14, 5),
282 GATE(ACLK_GIC_ADB400_CORE_B_2_GIC, "aclk_core_adb400_core_b_2_gic", "armclkb", 14, 4),
283 GATE(ACLK_GIC_ADB400_GIC_2_CORE_B, "aclk_core_adb400_gic_2_core_b", "armclkb", 14, 3),
284 GATE(0, "pclk_dbg_cxcs_pd_core_b", "pclk_dbg_core_b", 14, 2),
285 GATE(0, "clk_dbg_pd_core_b", "armclkb", 14, 1),
286 /* 0 unused */
287
288 /* CRU_CLKGATE_CON15 */
289 /* 15 - 8 unused */
290 GATE(ACLK_CCI_GRF, "aclk_cci_grf", "aclk_cci_pre", 15, 7),
291 GATE(0, "clk_dbg_noc", "clk_cs", 15, 6),
292 GATE(0, "clk_dbg_cxcs", "clk_cs", 15, 5),
293 GATE(ACLK_CCI_NOC1, "aclk_cci_noc1", "aclk_cci_pre", 15, 4),
294 GATE(ACLK_CCI_NOC0, "aclk_cci_noc0", "aclk_cci_pre", 15, 3),
295 GATE(ACLK_CCI, "aclk_cci", "aclk_cci_pre", 15, 2),
296 GATE(ACLK_ADB400M_PD_CORE_B, "aclk_adb400m_pd_core_b", "aclk_cci_pre", 15, 1),
297 GATE(ACLK_ADB400M_PD_CORE_L, "aclk_adb400m_pd_core_l", "aclk_cci_pre", 15, 0),
298
299 /* CRU_CLKGATE_CON16 */
300 /* 15 - 12 unused */
301 GATE(HCLK_RGA_NOC, "hclk_rga_noc", "hclk_rga_pre", 16, 11),
302 GATE(HCLK_RGA, "hclk_rga", "hclk_rga_pre", 16, 10),
303 GATE(ACLK_RGA_NOC, "aclk_rga_noc", "aclk_rga_pre", 16, 9),
304 GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 16, 8),
305 /* 7 - 4 unused */
306 GATE(HCLK_IEP_NOC, "hclk_iep_noc", "hclk_iep_pre", 16, 3),
307 GATE(HCLK_IEP, "hclk_iep", "hclk_iep_pre", 16, 2),
308 GATE(ACLK_IEP_NOC, "aclk_iep_noc", "aclk_iep_pre", 16, 1),
309 GATE(ACLK_IEP, "aclk_iep", "aclk_iep_pre", 16, 0),
310
311 /* CRU_CLKGATE_CON17 */
312 /* 15 - 12 unused */
313 GATE(HCLK_VDU_NOC, "hclk_vdu_noc", "hclk_vdu_pre", 17, 11),
314 GATE(HCLK_VDU, "hclk_vdu", "hclk_vdu_pre", 17, 10),
315 GATE(ACLK_VDU_NOC, "aclk_vdu_noc", "aclk_vdu_pre", 17, 9),
316 GATE(ACLK_VDU, "aclk_vdu", "aclk_vdu_pre", 17, 8),
317 GATE(0, "hclk_vcodec_noc", "hclk_vcodec_pre", 17, 3),
318 GATE(HCLK_VCODEC, "hclk_vcodec", "hclk_vcodec_pre", 17, 2),
319 GATE(0, "aclk_vcodec_noc", "aclk_vcodec_pre", 17, 1),
320 GATE(ACLK_VCODEC, "aclk_vcodec", "aclk_vcodec_pre", 17, 0),
321
322 /* CRU_CLKGATE_CON18 */
323 GATE(PCLK_CIC, "pclk_cic", "pclk_ddr", 18, 15),
324 GATE(0, "clk_ddr_mon_timer", "xin24m", 18, 14),
325 GATE(0, "clk_ddr_mon", "clk_ddrc_div2", 18, 13),
326 GATE(PCLK_DDR_MON, "pclk_ddr_mon", "pclk_ddr", 18, 12),
327 GATE(0, "clk_ddr_cic", "clk_ddrc_div2", 18, 11),
328 GATE(PCLK_CENTER_MAIN_NOC, "pclk_center_main_noc", "pclk_ddr", 18, 10),
329 GATE(0, "clk_ddrcfg_msch1", "clk_ddrc_div2", 18, 9),
330 GATE(0, "clk_ddrphy1", "clk_ddrc_div2", 18, 8),
331 GATE(0, "clk_ddrphy_ctrl1", "clk_ddrc_div2", 18, 7),
332 GATE(0, "clk_ddrc1", "clk_ddrc_div2", 18, 6),
333 GATE(0, "clk_ddr1_msch", "clk_ddrc_div2", 18, 5),
334 GATE(0, "clk_ddrcfg_msch0", "clk_ddrc_div2", 18, 4),
335 GATE(0, "clk_ddrphy0", "clk_ddrc_div2", 18, 3),
336 GATE(0, "clk_ddrphy_ctrl0", "clk_ddrc_div2", 18, 2),
337 GATE(0, "clk_ddrc0", "clk_ddrc_div2", 18, 1),
338
339 /* CRU_CLKGATE_CON19 */
340 /* 15 - 3 unused */
341 GATE(PCLK_DDR_SGRF, "pclk_ddr_sgrf", "pclk_ddr", 19, 2),
342 GATE(ACLK_CENTER_PERI_NOC, "aclk_center_peri_noc", "aclk_center", 19, 1),
343 GATE(ACLK_CENTER_MAIN_NOC, "aclk_center_main_noc", "aclk_center", 19, 0),
344
345 /* CRU_CLKGATE_CON20 */
346 GATE(0, "hclk_ahb1tom", "hclk_perihp", 20, 15),
347 GATE(0, "pclk_perihp_noc", "pclk_perihp", 20, 14),
348 GATE(0, "hclk_perihp_noc", "hclk_perihp", 20, 13),
349 GATE(0, "aclk_perihp_noc", "aclk_perihp", 20, 12),
350 GATE(PCLK_PCIE, "pclk_pcie", "pclk_perihp", 20, 11),
351 GATE(ACLK_PCIE, "aclk_pcie", "aclk_perihp", 20, 10),
352 GATE(HCLK_HSIC, "hclk_hsic", "hclk_perihp", 20, 9),
353 GATE(HCLK_HOST1_ARB, "hclk_host1_arb", "hclk_perihp", 20, 8),
354 GATE(HCLK_HOST1, "hclk_host1", "hclk_perihp", 20, 7),
355 GATE(HCLK_HOST0_ARB, "hclk_host0_arb", "hclk_perihp", 20, 6),
356 GATE(HCLK_HOST0, "hclk_host0", "hclk_perihp", 20, 5),
357 GATE(PCLK_PERIHP_GRF, "pclk_perihp_grf", "pclk_perihp", 20, 4),
358 GATE(ACLK_PERF_PCIE, "aclk_perf_pcie", "aclk_perihp", 20, 2),
359 /* 1 - 0 unused */
360
361 /* CRU_CLKGATE_CON21 */
362 /* 15 - 10 unused */
363 GATE(PCLK_UPHY1_TCPD_G, "pclk_uphy1_tcpd_g", "pclk_alive", 21, 9),
364 GATE(PCLK_UPHY1_TCPHY_G, "pclk_uphy1_tcphy_g", "pclk_alive", 21, 8),
365 /* 7 unused */
366 GATE(PCLK_UPHY0_TCPD_G, "pclk_uphy0_tcpd_g", "pclk_alive", 21, 6),
367 GATE(PCLK_UPHY0_TCPHY_G, "pclk_uphy0_tcphy_g", "pclk_alive", 21, 5),
368 GATE(PCLK_USBPHY_MUX_G, "pclk_usbphy_mux_g", "pclk_alive", 21, 4),
369 GATE(SCLK_DPHY_RX0_CFG, "clk_dphy_rx0_cfg", "clk_mipidphy_cfg", 21, 3),
370 GATE(SCLK_DPHY_TX1RX1_CFG, "clk_dphy_tx1rx1_cfg", "clk_mipidphy_cfg", 21, 2),
371 GATE(SCLK_DPHY_TX0_CFG, "clk_dphy_tx0_cfg", "clk_mipidphy_cfg", 21, 1),
372 GATE(SCLK_DPHY_PLL, "clk_dphy_pll", "clk_mipidphy_ref", 21, 0),
373
374 /* CRU_CLKGATE_CON22 */
375 GATE(PCLK_EFUSE1024S, "pclk_efuse1024s", "pclk_perilp1", 22, 15),
376 GATE(PCLK_EFUSE1024NS, "pclk_efuse1024ns", "pclk_perilp1", 22, 14),
377 GATE(PCLK_TSADC, "pclk_tsadc", "pclk_perilp1", 22, 13),
378 GATE(PCLK_SARADC, "pclk_saradc", "pclk_perilp1", 22, 12),
379 GATE(PCLK_MAILBOX0, "pclk_mailbox0", "pclk_perilp1", 22, 11),
380 GATE(PCLK_I2C3, "pclk_i2c3", "pclk_perilp1", 22, 10),
381 GATE(PCLK_I2C2, "pclk_i2c2", "pclk_perilp1", 22, 9),
382 GATE(PCLK_I2C6, "pclk_i2c6", "pclk_perilp1", 22, 8),
383 GATE(PCLK_I2C5, "pclk_i2c5", "pclk_perilp1", 22, 7),
384 GATE(PCLK_I2C1, "pclk_i2c1", "pclk_perilp1", 22, 6),
385 GATE(PCLK_I2C7, "pclk_i2c7", "pclk_perilp1", 22, 5),
386 GATE(PCLK_UART3, "pclk_uart3", "pclk_perilp1", 22, 3),
387 GATE(PCLK_UART2, "pclk_uart2", "pclk_perilp1", 22, 2),
388 GATE(PCLK_UART1, "pclk_uart1", "pclk_perilp1", 22, 1),
389 GATE(PCLK_UART0, "pclk_uart0", "pclk_perilp1", 22, 0),
390
391 /* CRU_CLKGATE_CON23 */
392 /* 15 - 14 unused */
393 GATE(PCLK_SPI4, "pclk_spi4", "pclk_perilp1", 23, 13),
394 GATE(PCLK_SPI2, "pclk_spi2", "pclk_perilp1", 23, 12),
395 GATE(PCLK_SPI1, "pclk_spi1", "pclk_perilp1", 23, 11),
396 GATE(PCLK_SPI0, "pclk_spi0", "pclk_perilp1", 23, 10),
397 GATE(PCLK_DCF, "pclk_dcf", "pclk_perilp0", 23, 9),
398 GATE(ACLK_DCF, "aclk_dcf", "aclk_perilp0", 23, 8),
399 GATE(SCLK_INTMEM5, "clk_intmem5", "aclk_perilp0", 23, 7),
400 GATE(SCLK_INTMEM4, "clk_intmem4", "aclk_perilp0", 23, 6),
401 GATE(SCLK_INTMEM3, "clk_intmem3", "aclk_perilp0", 23, 5),
402 GATE(SCLK_INTMEM2, "clk_intmem2", "aclk_perilp0", 23, 4),
403 GATE(SCLK_INTMEM1, "clk_intmem1", "aclk_perilp0", 23, 3),
404 GATE(SCLK_INTMEM0, "clk_intmem0", "aclk_perilp0", 23, 2),
405 GATE(ACLK_TZMA, "aclk_tzma", "aclk_perilp0", 23, 1),
406 GATE(ACLK_INTMEM, "aclk_intmem", "aclk_perilp0", 23, 0),
407
408 /* CRU_CLKGATE_CON24 */
409 GATE(HCLK_S_CRYPTO1, "hclk_s_crypto1", "hclk_perilp0", 24, 15),
410 GATE(HCLK_M_CRYPTO1, "hclk_m_crypto1", "hclk_perilp0", 24, 14),
411 GATE(PCLK_PERIHP_GRF, "pclk_perilp_sgrf", "pclk_perilp1", 24, 13),
412 GATE(SCLK_M0_PERILP_DEC, "clk_m0_perilp_dec", "fclk_cm0s", 24, 11),
413 GATE(DCLK_M0_PERILP, "dclk_m0_perilp", "fclk_cm0s", 24, 10),
414 GATE(HCLK_M0_PERILP, "hclk_m0_perilp", "fclk_cm0s", 24, 9),
415 GATE(SCLK_M0_PERILP, "sclk_m0_perilp", "fclk_cm0s", 24, 8),
416 /* 7 - unused */
417 GATE(HCLK_S_CRYPTO0, "hclk_s_crypto0", "hclk_perilp0", 24, 6),
418 GATE(HCLK_M_CRYPTO0, "hclk_m_crypto0", "hclk_perilp0", 24, 5),
419 GATE(HCLK_ROM, "hclk_rom", "hclk_perilp0", 24, 4),
420 /* 3 - 0 unused */
421
422 /* CRU_CLKGATE_CON25 */
423 /* 15 - 13 unused */
424 GATE(0, "hclk_sdio_noc", "hclk_perilp1", 25, 12),
425 GATE(HCLK_M0_PERILP_NOC, "hclk_m0_perilp_noc", "fclk_cm0s", 25, 11),
426 GATE(0, "pclk_perilp1_noc", "pclk_perilp1", 25, 10),
427 GATE(0, "hclk_perilp1_noc", "hclk_perilp1", 25, 9),
428 GATE(HCLK_PERILP0_NOC, "hclk_perilp0_noc", "hclk_perilp0", 25, 8),
429 GATE(ACLK_PERILP0_NOC, "aclk_perilp0_noc", "aclk_perilp0", 25, 7),
430 GATE(ACLK_DMAC1_PERILP, "aclk_dmac1_perilp", "aclk_perilp0", 25, 6),
431 GATE(ACLK_DMAC0_PERILP, "aclk_dmac0_perilp", "aclk_perilp0", 25, 5),
432 /* 4 - 0 unused */
433
434 /* CRU_CLKGATE_CON26 */
435 /* 15 - 12 unused */
436 GATE(SCLK_TIMER11, "clk_timer11", "xin24m", 26, 11),
437 GATE(SCLK_TIMER10, "clk_timer10", "xin24m", 26, 10),
438 GATE(SCLK_TIMER09, "clk_timer09", "xin24m", 26, 9),
439 GATE(SCLK_TIMER08, "clk_timer08", "xin24m", 26, 8),
440 GATE(SCLK_TIMER07, "clk_timer07", "xin24m", 26, 7),
441 GATE(SCLK_TIMER06, "clk_timer06", "xin24m", 26, 6),
442 GATE(SCLK_TIMER05, "clk_timer05", "xin24m", 26, 5),
443 GATE(SCLK_TIMER04, "clk_timer04", "xin24m", 26, 4),
444 GATE(SCLK_TIMER03, "clk_timer03", "xin24m", 26, 3),
445 GATE(SCLK_TIMER02, "clk_timer02", "xin24m", 26, 2),
446 GATE(SCLK_TIMER01, "clk_timer01", "xin24m", 26, 1),
447 GATE(SCLK_TIMER00, "clk_timer00", "xin24m", 26, 0),
448
449 /* CRU_CLKGATE_CON27 */
450 /* 15 - 9 unused */
451 GATE(ACLK_ISP1_WRAPPER, "aclk_isp1_wrapper", "hclk_isp1", 27, 8),
452 GATE(HCLK_ISP1_WRAPPER, "hclk_isp1_wrapper", "aclk_isp0", 27, 7),
453 GATE(PCLK_ISP1_WRAPPER, "pclkin_isp1_wrapper", "pclkin_cif", 27, 6),
454 GATE(ACLK_ISP0_WRAPPER, "aclk_isp0_wrapper", "aclk_isp0", 27, 5),
455 GATE(HCLK_ISP0_WRAPPER, "hclk_isp0_wrapper", "hclk_isp0", 27, 4),
456 GATE(ACLK_ISP1_NOC, "aclk_isp1_noc", "aclk_isp1", 27, 3),
457 GATE(HCLK_ISP1_NOC, "hclk_isp1_noc", "hclk_isp1", 27, 2),
458 GATE(ACLK_ISP0_NOC, "aclk_isp0_noc", "aclk_isp0", 27, 1),
459 GATE(HCLK_ISP0_NOC, "hclk_isp0_noc", "hclk_isp0", 27, 0),
460
461 /* CRU_CLKGATE_CON28 */
462 /* 15 - 8 unused */
463 GATE(ACLK_VOP1, "aclk_vop1", "aclk_vop1_pre", 28, 7),
464 GATE(HCLK_VOP1, "hclk_vop1", "hclk_vop1_pre", 28, 6),
465 GATE(ACLK_VOP1_NOC, "aclk_vop1_noc", "aclk_vop1_pre", 28, 5),
466 GATE(HCLK_VOP1_NOC, "hclk_vop1_noc", "hclk_vop1_pre", 28, 4),
467 GATE(ACLK_VOP0, "aclk_vop0", "aclk_vop0_pre", 28, 3),
468 GATE(HCLK_VOP0, "hclk_vop0", "hclk_vop0_pre", 28, 2),
469 GATE(ACLK_VOP0_NOC, "aclk_vop0_noc", "aclk_vop0_pre", 28, 1),
470 GATE(HCLK_VOP0_NOC, "hclk_vop0_noc", "hclk_vop0_pre", 28, 0),
471
472 /* CRU_CLKGATE_CON29 */
473 /* 15 - 13 unused */
474 GATE(PCLK_VIO_GRF, "pclk_vio_grf", "pclk_vio", 29, 12),
475 GATE(PCLK_GASKET, "pclk_gasket", "pclk_hdcp", 29, 11),
476 GATE(ACLK_HDCP22, "aclk_hdcp22", "aclk_hdcp", 29, 10),
477 GATE(HCLK_HDCP22, "hclk_hdcp22", "hclk_hdcp", 29, 9),
478 GATE(PCLK_HDCP22, "pclk_hdcp22", "pclk_hdcp", 29, 8),
479 GATE(PCLK_DP_CTRL, "pclk_dp_ctrl", "pclk_hdcp", 29, 7),
480 GATE(PCLK_HDMI_CTRL, "pclk_hdmi_ctrl", "pclk_hdcp", 29, 6),
481 GATE(HCLK_HDCP_NOC, "hclk_hdcp_noc", "hclk_hdcp", 29, 5),
482 GATE(ACLK_HDCP_NOC, "aclk_hdcp_noc", "aclk_hdcp", 29, 4),
483 GATE(PCLK_HDCP_NOC, "pclk_hdcp_noc", "pclk_hdcp", 29, 3),
484 GATE(PCLK_MIPI_DSI1, "pclk_mipi_dsi1", "pclk_vio", 29, 2),
485 GATE(PCLK_MIPI_DSI0, "pclk_mipi_dsi0", "pclk_vio", 29, 1),
486 GATE(ACLK_VIO_NOC, "aclk_vio_noc", "aclk_vio", 29, 0),
487
488 /* CRU_CLKGATE_CON30 */
489 /* 15 - 12 unused */
490 GATE(ACLK_GPU_GRF, "aclk_gpu_grf", "aclk_gpu_pre", 30, 11),
491 GATE(ACLK_PERF_GPU, "aclk_perf_gpu", "aclk_gpu_pre", 30, 10),
492 /* 9 unused */
493 GATE(ACLK_GPU, "aclk_gpu", "aclk_gpu_pre", 30, 8),
494 /* 7 - 5 unused */
495 GATE(ACLK_USB3_GRF, "aclk_usb3_grf", "aclk_usb3", 30, 4),
496 GATE(ACLK_USB3_RKSOC_AXI_PERF, "aclk_usb3_rksoc_axi_perf", "aclk_usb3", 30, 3),
497 GATE(ACLK_USB3OTG1, "aclk_usb3otg1", "aclk_usb3", 30, 2),
498 GATE(ACLK_USB3OTG0, "aclk_usb3otg0", "aclk_usb3", 30, 1),
499 GATE(ACLK_USB3_NOC, "aclk_usb3_noc", "aclk_usb3", 30, 0),
500
501 /* CRU_CLKGATE_CON31 */
502 /* 15 - 11 unused */
503 GATE(PCLK_SGRF, "pclk_sgrf", "pclk_alive", 31, 10),
504 GATE(PCLK_PMU_INTR_ARB, "pclk_pmu_intr_arb", "pclk_alive", 31, 9),
505 GATE(PCLK_HSICPHY, "pclk_hsicphy", "pclk_perihp", 31, 8),
506 GATE(PCLK_TIMER1, "pclk_timer1", "pclk_alive", 31, 7),
507 GATE(PCLK_TIMER0, "pclk_timer0", "pclk_alive", 31, 6),
508 GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_alive", 31, 5),
509 GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_alive", 31, 4),
510 GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_alive", 31, 3),
511 GATE(PCLK_INTR_ARB, "pclk_intr_arb", "pclk_alive", 31, 2),
512 GATE(PCLK_GRF, "pclk_grf", "pclk_alive", 31, 1),
513 /* 0 unused */
514
515 /* CRU_CLKGATE_CON32 */
516 /* 15 - 14 unused */
517 GATE(PCLK_EDP_CTRL, "pclk_edp_ctrl", "pclk_edp", 32, 13),
518 GATE(PCLK_EDP_NOC, "pclk_edp_noc", "pclk_edp", 32, 12),
519 /* 11 unused */
520 GATE(ACLK_EMMC_GRF, "aclk_emmcgrf", "aclk_emmc", 32, 10),
521 GATE(ACLK_EMMC_NOC, "aclk_emmc_noc", "aclk_emmc", 32, 9),
522 GATE(ACLK_EMMC_CORE, "aclk_emmccore", "aclk_emmc", 32, 8),
523 /* 7 - 5 unused */
524 GATE(ACLK_PERF_GMAC, "aclk_perf_gmac", "aclk_gmac_pre", 32, 4),
525 GATE(PCLK_GMAC_NOC, "pclk_gmac_noc", "pclk_gmac_pre", 32, 3),
526 GATE(PCLK_GMAC, "pclk_gmac", "pclk_gmac_pre", 32, 2),
527 GATE(ACLK_GMAC_NOC, "aclk_gmac_noc", "aclk_gmac_pre", 32, 1),
528 GATE(ACLK_GMAC, "aclk_gmac", "aclk_gmac_pre", 32, 0),
529
530 /* CRU_CLKGATE_CON33 */
531 /* 15 - 10 unused */
532 GATE(0, "hclk_sdmmc_noc", "hclk_sd", 33, 9),
533 GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_sd", 33, 8),
534 GATE(ACLK_GIC_ADB400_GIC_2_CORE_B, "aclk_gic_adb400_gic_2_core_b", "aclk_gic_pre", 33, 5),
535 GATE(ACLK_GIC_ADB400_GIC_2_CORE_L, "aclk_gic_adb400_gic_2_core_l", "aclk_gic_pre", 33, 4),
536 GATE(ACLK_GIC_ADB400_CORE_B_2_GIC, "aclk_gic_adb400_core_b_2_gic", "aclk_gic_pre", 33, 3),
537 GATE(ACLK_GIC_ADB400_CORE_L_2_GIC, "aclk_gic_adb400_core_l_2_gic", "aclk_gic_pre", 33, 2),
538 GATE(ACLK_GIC_NOC, "aclk_gic_noc", "aclk_gic_pre", 33, 1),
539 GATE(ACLK_GIC, "aclk_gic", "aclk_gic_pre", 33, 0),
540
541 /* CRU_CLKGATE_CON34 */
542 /* 15 - 7 unused */
543 GATE(0, "hclk_sdioaudio_noc", "hclk_perilp1", 34, 6),
544 GATE(PCLK_SPI5, "pclk_spi5", "hclk_perilp1", 34, 5),
545 GATE(HCLK_SDIO, "hclk_sdio", "hclk_perilp1", 34, 4),
546 GATE(HCLK_SPDIF, "hclk_spdif", "hclk_perilp1", 34, 3),
547 GATE(HCLK_I2S2_8CH, "hclk_i2s2", "hclk_perilp1", 34, 2),
548 GATE(HCLK_I2S1_8CH, "hclk_i2s1", "hclk_perilp1", 34, 1),
549 GATE(HCLK_I2S0_8CH, "hclk_i2s0", "hclk_perilp1", 34, 0),
550 };
551
552 #define PLL_RATE(_hz, _ref, _fb, _post1, _post2, _dspd) \
553 { \
554 .freq = _hz, \
555 .refdiv = _ref, \
556 .fbdiv = _fb, \
557 .postdiv1 = _post1, \
558 .postdiv2 = _post2, \
559 .dsmpd = _dspd, \
560 }
561
562 static struct rk_clk_pll_rate rk3399_pll_rates[] = {
563 /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
564 PLL_RATE(2208000000, 1, 92, 1, 1, 1),
565 PLL_RATE(2184000000, 1, 91, 1, 1, 1),
566 PLL_RATE(2160000000, 1, 90, 1, 1, 1),
567 PLL_RATE(2136000000, 1, 89, 1, 1, 1),
568 PLL_RATE(2112000000, 1, 88, 1, 1, 1),
569 PLL_RATE(2088000000, 1, 87, 1, 1, 1),
570 PLL_RATE(2064000000, 1, 86, 1, 1, 1),
571 PLL_RATE(2040000000, 1, 85, 1, 1, 1),
572 PLL_RATE(2016000000, 1, 84, 1, 1, 1),
573 PLL_RATE(1992000000, 1, 83, 1, 1, 1),
574 PLL_RATE(1968000000, 1, 82, 1, 1, 1),
575 PLL_RATE(1944000000, 1, 81, 1, 1, 1),
576 PLL_RATE(1920000000, 1, 80, 1, 1, 1),
577 PLL_RATE(1896000000, 1, 79, 1, 1, 1),
578 PLL_RATE(1872000000, 1, 78, 1, 1, 1),
579 PLL_RATE(1848000000, 1, 77, 1, 1, 1),
580 PLL_RATE(1824000000, 1, 76, 1, 1, 1),
581 PLL_RATE(1800000000, 1, 75, 1, 1, 1),
582 PLL_RATE(1776000000, 1, 74, 1, 1, 1),
583 PLL_RATE(1752000000, 1, 73, 1, 1, 1),
584 PLL_RATE(1728000000, 1, 72, 1, 1, 1),
585 PLL_RATE(1704000000, 1, 71, 1, 1, 1),
586 PLL_RATE(1680000000, 1, 70, 1, 1, 1),
587 PLL_RATE(1656000000, 1, 69, 1, 1, 1),
588 PLL_RATE(1632000000, 1, 68, 1, 1, 1),
589 PLL_RATE(1608000000, 1, 67, 1, 1, 1),
590 PLL_RATE(1600000000, 3, 200, 1, 1, 1),
591 PLL_RATE(1584000000, 1, 66, 1, 1, 1),
592 PLL_RATE(1560000000, 1, 65, 1, 1, 1),
593 PLL_RATE(1536000000, 1, 64, 1, 1, 1),
594 PLL_RATE(1512000000, 1, 63, 1, 1, 1),
595 PLL_RATE(1488000000, 1, 62, 1, 1, 1),
596 PLL_RATE(1464000000, 1, 61, 1, 1, 1),
597 PLL_RATE(1440000000, 1, 60, 1, 1, 1),
598 PLL_RATE(1416000000, 1, 59, 1, 1, 1),
599 PLL_RATE(1392000000, 1, 58, 1, 1, 1),
600 PLL_RATE(1368000000, 1, 57, 1, 1, 1),
601 PLL_RATE(1344000000, 1, 56, 1, 1, 1),
602 PLL_RATE(1320000000, 1, 55, 1, 1, 1),
603 PLL_RATE(1296000000, 1, 54, 1, 1, 1),
604 PLL_RATE(1272000000, 1, 53, 1, 1, 1),
605 PLL_RATE(1248000000, 1, 52, 1, 1, 1),
606 PLL_RATE(1200000000, 1, 50, 1, 1, 1),
607 PLL_RATE(1188000000, 2, 99, 1, 1, 1),
608 PLL_RATE(1104000000, 1, 46, 1, 1, 1),
609 PLL_RATE(1100000000, 12, 550, 1, 1, 1),
610 PLL_RATE(1008000000, 1, 84, 2, 1, 1),
611 PLL_RATE(1000000000, 1, 125, 3, 1, 1),
612 PLL_RATE( 984000000, 1, 82, 2, 1, 1),
613 PLL_RATE( 960000000, 1, 80, 2, 1, 1),
614 PLL_RATE( 936000000, 1, 78, 2, 1, 1),
615 PLL_RATE( 912000000, 1, 76, 2, 1, 1),
616 PLL_RATE( 900000000, 4, 300, 2, 1, 1),
617 PLL_RATE( 888000000, 1, 74, 2, 1, 1),
618 PLL_RATE( 864000000, 1, 72, 2, 1, 1),
619 PLL_RATE( 840000000, 1, 70, 2, 1, 1),
620 PLL_RATE( 816000000, 1, 68, 2, 1, 1),
621 PLL_RATE( 800000000, 1, 100, 3, 1, 1),
622 PLL_RATE( 700000000, 6, 350, 2, 1, 1),
623 PLL_RATE( 696000000, 1, 58, 2, 1, 1),
624 PLL_RATE( 676000000, 3, 169, 2, 1, 1),
625 PLL_RATE( 600000000, 1, 75, 3, 1, 1),
626 PLL_RATE( 594000000, 1, 99, 4, 1, 1),
627 PLL_RATE( 533250000, 8, 711, 4, 1, 1),
628 PLL_RATE( 504000000, 1, 63, 3, 1, 1),
629 PLL_RATE( 500000000, 6, 250, 2, 1, 1),
630 PLL_RATE( 408000000, 1, 68, 2, 2, 1),
631 PLL_RATE( 312000000, 1, 52, 2, 2, 1),
632 PLL_RATE( 297000000, 1, 99, 4, 2, 1),
633 PLL_RATE( 216000000, 1, 72, 4, 2, 1),
634 PLL_RATE( 148500000, 1, 99, 4, 4, 1),
635 PLL_RATE( 106500000, 1, 71, 4, 4, 1),
636 PLL_RATE( 96000000, 1, 64, 4, 4, 1),
637 PLL_RATE( 74250000, 2, 99, 4, 4, 1),
638 PLL_RATE( 65000000, 1, 65, 6, 4, 1),
639 PLL_RATE( 54000000, 1, 54, 6, 4, 1),
640 PLL_RATE( 27000000, 1, 27, 6, 4, 1),
641 {},
642 };
643
644 static struct rk_clk_armclk_rates rk3399_cpu_l_rates[] = {
645 {1800000000, 1},
646 {1704000000, 1},
647 {1608000000, 1},
648 {1512000000, 1},
649 {1488000000, 1},
650 {1416000000, 1},
651 {1200000000, 1},
652 {1008000000, 1},
653 { 816000000, 1},
654 { 696000000, 1},
655 { 600000000, 1},
656 { 408000000, 1},
657 { 312000000, 1},
658 { 216000000, 1},
659 { 96000000, 1},
660 };
661
662 static struct rk_clk_armclk_rates rk3399_cpu_b_rates[] = {
663 {2208000000, 1},
664 {2184000000, 1},
665 {2088000000, 1},
666 {2040000000, 1},
667 {2016000000, 1},
668 {1992000000, 1},
669 {1896000000, 1},
670 {1800000000, 1},
671 {1704000000, 1},
672 {1608000000, 1},
673 {1512000000, 1},
674 {1488000000, 1},
675 {1416000000, 1},
676 {1200000000, 1},
677 {1008000000, 1},
678 { 816000000, 1},
679 { 696000000, 1},
680 { 600000000, 1},
681 { 408000000, 1},
682 { 312000000, 1},
683 { 216000000, 1},
684 { 96000000, 1},
685 };
686
687 /* Standard PLL. */
688 #define PLL(_id, _name, _base) \
689 { \
690 .type = RK3399_CLK_PLL, \
691 .clk.pll = &(struct rk_clk_pll_def) { \
692 .clkdef.id = _id, \
693 .clkdef.name = _name, \
694 .clkdef.parent_names = pll_src_p, \
695 .clkdef.parent_cnt = nitems(pll_src_p), \
696 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \
697 .base_offset = _base, \
698 .rates = rk3399_pll_rates, \
699 }, \
700 }
701
702 #define PLIST(_name) static const char *_name[]
703 PLIST(pll_src_p) = {"xin24m", "xin32k"};
704
705 PLIST(armclkl_p) = {"clk_core_l_lpll_src", "clk_core_l_bpll_src",
706 "clk_core_l_dpll_src", "clk_core_l_gpll_src"};
707 PLIST(armclkb_p) = {"clk_core_b_lpll_src", "clk_core_b_bpll_src",
708 "clk_core_b_dpll_src", "clk_core_b_gpll_src"};
709 PLIST(ddrclk_p) = {"clk_ddrc_lpll_src", "clk_ddrc_bpll_src",
710 "clk_ddrc_dpll_src", "clk_ddrc_gpll_src"};
711 PLIST(pll_src_cpll_gpll_p) = {"cpll", "gpll"};
712 PLIST(pll_src_cpll_gpll_ppll_p) = {"cpll", "gpll", "ppll"};
713 PLIST(pll_src_cpll_gpll_upll_p) = {"cpll", "gpll", "upll"};
714 PLIST(pll_src_npll_cpll_gpll_p) = {"npll", "cpll", "gpll"};
715 PLIST(pll_src_cpll_gpll_npll_npll_p) = {"cpll", "gpll", "npll", "npll"};
716 PLIST(pll_src_cpll_gpll_npll_ppll_p) = {"cpll", "gpll", "npll", "ppll" };
717 PLIST(pll_src_cpll_gpll_npll_24m_p) = {"cpll", "gpll", "npll", "xin24m" };
718 PLIST(pll_src_cpll_gpll_npll_usbphy480m_p)= {"cpll", "gpll", "npll", "clk_usbphy_480m" };
719 PLIST(pll_src_ppll_cpll_gpll_npll_upll_p) = { "ppll", "cpll", "gpll", "npll", "upll" };
720 PLIST(pll_src_cpll_gpll_npll_upll_24m_p)= { "cpll", "gpll", "npll", "upll", "xin24m" };
721 PLIST(pll_src_cpll_gpll_npll_ppll_upll_24m_p) = { "cpll", "gpll", "npll", "ppll", "upll", "xin24m" };
722 PLIST(pll_src_vpll_cpll_gpll_gpll_p) = {"vpll", "cpll", "gpll", "gpll"};
723 PLIST(pll_src_vpll_cpll_gpll_npll_p) = {"vpll", "cpll", "gpll", "npll"};
724
725 PLIST(aclk_cci_p) = {"cpll_aclk_cci_src", "gpll_aclk_cci_src",
726 "npll_aclk_cci_src", "vpll_aclk_cci_src"};
727 PLIST(cci_trace_p) = {"cpll_cci_trace","gpll_cci_trace"};
728 PLIST(cs_p)= {"cpll_cs", "gpll_cs", "npll_cs","npll_cs"};
729 PLIST(aclk_perihp_p)= {"cpll_aclk_perihp_src", "gpll_aclk_perihp_src" };
730 PLIST(dclk_vop0_p) = {"dclk_vop0_div", "dclk_vop0_frac"};
731 PLIST(dclk_vop1_p)= {"dclk_vop1_div", "dclk_vop1_frac"};
732
733 PLIST(clk_cif_p) = {"clk_cifout_src", "xin24m"};
734
735 PLIST(pll_src_24m_usbphy480m_p) = { "xin24m", "clk_usbphy_480m"};
736 PLIST(pll_src_24m_pciephy_p) = { "xin24m", "clk_pciephy_ref100m"};
737 PLIST(pll_src_24m_32k_cpll_gpll_p)= {"xin24m", "xin32k", "cpll", "gpll"};
738 PLIST(pciecore_cru_phy_p) = {"clk_pcie_core_cru", "clk_pcie_core_phy"};
739
740 PLIST(aclk_emmc_p) = { "cpll_aclk_emmc_src", "gpll_aclk_emmc_src"};
741
742 PLIST(aclk_perilp0_p) = { "cpll_aclk_perilp0_src",
743 "gpll_aclk_perilp0_src" };
744
745 PLIST(fclk_cm0s_p) = { "cpll_fclk_cm0s_src",
746 "gpll_fclk_cm0s_src" };
747
748 PLIST(hclk_perilp1_p) = { "cpll_hclk_perilp1_src",
749 "gpll_hclk_perilp1_src" };
750
751 PLIST(clk_testout1_p) = { "clk_testout1_pll_src", "xin24m" };
752 PLIST(clk_testout2_p) = { "clk_testout2_pll_src", "xin24m" };
753
754 PLIST(usbphy_480m_p) = { "clk_usbphy0_480m_src",
755 "clk_usbphy1_480m_src" };
756 PLIST(aclk_gmac_p) = { "cpll_aclk_gmac_src",
757 "gpll_aclk_gmac_src" };
758 PLIST(rmii_p) = { "clk_gmac", "clkin_gmac" };
759 PLIST(spdif_p) = { "clk_spdif_div", "clk_spdif_frac",
760 "clkin_i2s", "xin12m" };
761 PLIST(i2s0_p) = { "clk_i2s0_div", "clk_i2s0_frac",
762 "clkin_i2s", "xin12m" };
763 PLIST(i2s1_p) = { "clk_i2s1_div", "clk_i2s1_frac",
764 "clkin_i2s", "xin12m" };
765 PLIST(i2s2_p) = { "clk_i2s2_div", "clk_i2s2_frac",
766 "clkin_i2s", "xin12m" };
767 PLIST(i2sch_p) = {"clk_i2s0", "clk_i2s1", "clk_i2s2"};
768 PLIST(i2sout_p) = {"clk_i2sout_src", "xin12m"};
769
770 PLIST(uart0_p)= {"clk_uart0_div", "clk_uart0_frac", "xin24m"};
771 PLIST(uart1_p)= {"clk_uart1_div", "clk_uart1_frac", "xin24m"};
772 PLIST(uart2_p)= {"clk_uart2_div", "clk_uart2_frac", "xin24m"};
773 PLIST(uart3_p)= {"clk_uart3_div", "clk_uart3_frac", "xin24m"};
774
775 static struct rk_clk rk3399_clks[] = {
776 /* External clocks */
777 LINK("xin24m"),
778 FRATE(0, "xin32k", 32768),
779 FFACT(0, "xin12m", "xin24m", 1, 2),
780 FRATE(0, "clkin_i2s", 0),
781 FRATE(0, "pclkin_cif", 0),
782 LINK("clk_usbphy0_480m"),
783 LINK("clk_usbphy1_480m"),
784 LINK("clkin_gmac"),
785 FRATE(0, "clk_pcie_core_phy", 0),
786 FFACT(0, "clk_ddrc_div2", "clk_ddrc", 1, 2),
787
788 /* PLLs */
789 PLL(PLL_APLLL, "lpll", 0x00),
790 PLL(PLL_APLLB, "bpll", 0x20),
791 PLL(PLL_DPLL, "dpll", 0x40),
792 PLL(PLL_CPLL, "cpll", 0x60),
793 PLL(PLL_GPLL, "gpll", 0x80),
794 PLL(PLL_NPLL, "npll", 0xA0),
795 PLL(PLL_VPLL, "vpll", 0xC0),
796
797 /* CRU_CLKSEL_CON0 */
798 CDIV(0, "aclkm_core_l_c", "armclkl", 0,
799 0, 8, 5),
800 ARMDIV(ARMCLKL, "armclkl", armclkl_p, rk3399_cpu_l_rates,
801 0, 0, 5, 6, 2, 0, 3),
802 /* CRU_CLKSEL_CON1 */
803 CDIV(0, "pclk_dbg_core_l_c", "armclkl", 0,
804 1, 8, 5),
805 CDIV(0, "atclk_core_l_c", "armclkl", 0,
806 1, 0, 5),
807
808 /* CRU_CLKSEL_CON2 */
809 CDIV(0, "aclkm_core_b_c", "armclkb", 0,
810 2, 8, 5),
811 ARMDIV(ARMCLKB, "armclkb", armclkb_p, rk3399_cpu_b_rates,
812 2, 0, 5, 6, 2, 1, 3),
813
814 /* CRU_CLKSEL_CON3 */
815 CDIV(0, "pclken_dbg_core_b", "pclk_dbg_core_b", 0,
816 3, 13, 2),
817 CDIV(0, "pclk_dbg_core_b_c", "armclkb", 0,
818 3, 8, 5),
819 CDIV(0, "atclk_core_b_c", "armclkb", 0,
820 3, 0, 5),
821
822 /* CRU_CLKSEL_CON4 */
823 COMP(0, "clk_cs", cs_p, 0,
824 4, 0, 5, 6, 2),
825
826 /* CRU_CLKSEL_CON5 */
827 COMP(0, "clk_cci_trace_c", cci_trace_p, 0,
828 5, 8, 5, 15, 1),
829 COMP(0, "aclk_cci_pre_c", aclk_cci_p, 0,
830 5, 0, 5, 6, 2),
831
832 /* CRU_CLKSEL_CON6 */
833 COMP(0, "pclk_ddr_c", pll_src_cpll_gpll_p, 0,
834 6, 8, 5, 15, 1),
835 COMP(SCLK_DDRC, "clk_ddrc", ddrclk_p, 0,
836 6, 0, 3, 4, 2),
837
838 /* CRU_CLKSEL_CON7 */
839 CDIV(0, "hclk_vcodec_pre_c", "aclk_vcodec_pre", 0,
840 7, 8, 5),
841 COMP(0, "aclk_vcodec_pre_c", pll_src_cpll_gpll_npll_ppll_p, 0,
842 7, 0, 5, 6, 2),
843
844 /* CRU_CLKSEL_CON8 */
845 CDIV(0, "hclk_vdu_pre_c", "aclk_vdu_pre", 0,
846 8, 8, 5),
847 COMP(0, "aclk_vdu_pre_c", pll_src_cpll_gpll_npll_ppll_p, 0,
848 8, 0, 5, 6, 2),
849
850 /* CRU_CLKSEL_CON9 */
851 COMP(0, "clk_vdu_ca_c", pll_src_cpll_gpll_npll_npll_p, 0,
852 9, 8, 5, 14, 2),
853 COMP(0, "clk_vdu_core_c", pll_src_cpll_gpll_npll_npll_p, 0,
854 9, 0, 5, 6, 2),
855
856 /* CRU_CLKSEL_CON10 */
857 CDIV(0, "hclk_iep_pre_c", "aclk_iep_pre", 0,
858 10, 8, 5),
859 COMP(0, "aclk_iep_pre_c", pll_src_cpll_gpll_npll_ppll_p, 0,
860 10, 0, 5, 6, 2),
861
862 /* CRU_CLKSEL_CON11 */
863 CDIV(0, "hclk_rga_pre_c", "aclk_rga_pre", 0,
864 11, 8, 5),
865 COMP(0, "aclk_rga_pre_c", pll_src_cpll_gpll_npll_ppll_p, 0,
866 11, 0, 5, 6, 2),
867
868 /* CRU_CLKSEL_CON12 */
869 COMP(0, "aclk_center_c", pll_src_cpll_gpll_npll_npll_p, 0,
870 12, 8, 5, 14, 2),
871 COMP(SCLK_RGA_CORE, "clk_rga_core_c", pll_src_cpll_gpll_npll_ppll_p, 0,
872 12, 0, 5, 6, 2),
873
874 /* CRU_CLKSEL_CON13 */
875 COMP(0, "hclk_sd_c", pll_src_cpll_gpll_p, 0,
876 13, 8, 5, 15, 1),
877 COMP(0, "aclk_gpu_pre_c", pll_src_ppll_cpll_gpll_npll_upll_p, 0,
878 13, 0, 5, 5, 3),
879
880 /* CRU_CLKSEL_CON14 */
881 MUX(0, "upll", pll_src_24m_usbphy480m_p, 0,
882 14, 15, 1),
883 CDIV(0, "pclk_perihp_c", "aclk_perihp", 0,
884 14, 12, 2),
885 CDIV(0, "hclk_perihp_c", "aclk_perihp", 0,
886 14, 8, 2),
887 MUX(0, "clk_usbphy_480m", usbphy_480m_p, 0,
888 14, 6, 1),
889 COMP(0, "aclk_perihp_c", aclk_perihp_p, 0,
890 14, 0, 5, 7, 1),
891
892 /* CRU_CLKSEL_CON15 */
893 COMP(0, "clk_sdio_c", pll_src_cpll_gpll_npll_ppll_upll_24m_p, 0,
894 15, 0, 7, 8, 3),
895
896 /* CRU_CLKSEL_CON16 */
897 COMP(0, "clk_sdmmc_c", pll_src_cpll_gpll_npll_ppll_upll_24m_p, 0,
898 16, 0, 7, 8, 3),
899
900 /* CRU_CLKSEL_CON17 */
901 COMP(0, "clk_pcie_pm_c", pll_src_cpll_gpll_npll_24m_p, 0,
902 17, 0, 7, 8, 3),
903
904 /* CRU_CLKSEL_CON18 */
905 CDIV(0, "clk_pciephy_ref100m_c", "npll", 0,
906 18, 11, 5),
907 MUX(SCLK_PCIEPHY_REF, "clk_pciephy_ref", pll_src_24m_pciephy_p, 0,
908 18, 10, 1),
909 MUX(SCLK_PCIE_CORE, "clk_pcie_core", pciecore_cru_phy_p, 0,
910 18, 7, 1),
911 COMP(0, "clk_pcie_core_cru_c", pll_src_cpll_gpll_npll_npll_p, 0,
912 18, 0, 7, 8, 2),
913
914 /* CRU_CLKSEL_CON19 */
915 CDIV(0, "pclk_gmac_pre_c", "aclk_gmac_pre", 0,
916 19, 8, 3),
917 MUX(SCLK_RMII_SRC, "clk_rmii_src",rmii_p, 0,
918 19, 4, 1),
919 MUX(SCLK_HSICPHY, "clk_hsicphy_c", pll_src_cpll_gpll_npll_usbphy480m_p, 0,
920 19, 0, 2),
921
922 /* CRU_CLKSEL_CON20 */
923 COMP(0, "clk_gmac_c", pll_src_cpll_gpll_npll_npll_p, 0,
924 20, 8, 5, 14, 2),
925 COMP(0, "aclk_gmac_pre_c", aclk_gmac_p, 0,
926 20, 0, 5, 7, 1),
927
928 /* CRU_CLKSEL_CON21 */
929 COMP(ACLK_EMMC, "aclk_emmc", aclk_emmc_p, 0,
930 21, 0, 5, 7, 1),
931
932 /* CRU_CLKSEL_CON22 */
933 COMP(0, "clk_emmc_c", pll_src_cpll_gpll_npll_upll_24m_p, 0,
934 22, 0, 7, 8, 3),
935
936 /* CRU_CLKSEL_CON23 */
937 CDIV(0, "pclk_perilp0_c", "aclk_perilp0", 0,
938 23, 12, 3),
939 CDIV(0, "hclk_perilp0_c", "aclk_perilp0", 0,
940 23, 8, 2),
941 COMP(0, "aclk_perilp0_c", aclk_perilp0_p, 0,
942 23, 0, 5, 7, 1),
943
944 /* CRU_CLKSEL_CON24 */
945 COMP(0, "fclk_cm0s_c", fclk_cm0s_p, 0,
946 24, 8, 5, 15, 1),
947 COMP(0, "clk_crypto0_c", pll_src_cpll_gpll_ppll_p, 0,
948 24, 0, 5, 6, 2),
949
950 /* CRU_CLKSEL_CON25 */
951 CDIV(0, "pclk_perilp1_c", "hclk_perilp1", 0,
952 25, 8, 3),
953 COMP(HCLK_PERILP1, "hclk_perilp1", hclk_perilp1_p, 0,
954 25, 0, 5, 7, 1),
955
956 /* CRU_CLKSEL_CON26 */
957 CDIV(0, "clk_saradc_c", "xin24m", 0,
958 26, 8, 8),
959 COMP(0, "clk_crypto1_c", pll_src_cpll_gpll_ppll_p, 0,
960 26, 0, 5, 6, 2),
961
962 /* CRU_CLKSEL_CON27 */
963 COMP(0, "clk_tsadc_c", pll_src_p, 0,
964 27, 0, 10, 15, 1),
965
966 /* CRU_CLKSEL_CON28 */
967 MUX(0, "clk_i2s0_mux", i2s0_p, RK_CLK_MUX_REPARENT,
968 28, 8, 2),
969 COMP(0, "clk_i2s0_div_c", pll_src_cpll_gpll_p, 0,
970 28, 0, 7, 7, 1),
971
972 /* CRU_CLKSEL_CON29 */
973 MUX(0, "clk_i2s1_mux", i2s1_p, RK_CLK_MUX_REPARENT,
974 29, 8, 2),
975 COMP(0, "clk_i2s1_div_c", pll_src_cpll_gpll_p, 0,
976 29, 0, 7, 7, 1),
977
978 /* CRU_CLKSEL_CON30 */
979 MUX(0, "clk_i2s2_mux", i2s2_p, RK_CLK_MUX_REPARENT,
980 30, 8, 2),
981 COMP(0, "clk_i2s2_div_c", pll_src_cpll_gpll_p, 0,
982 30, 0, 7, 7, 1),
983
984 /* CRU_CLKSEL_CON31 */
985 MUX(0, "clk_i2sout_c", i2sout_p, 0,
986 31, 2, 1),
987 MUX(0, "clk_i2sout_src", i2sch_p, 0,
988 31, 0, 2),
989
990 /* CRU_CLKSEL_CON32 */
991 COMP(0, "clk_spdif_rec_dptx_c", pll_src_cpll_gpll_p, 0,
992 32, 8, 5, 15, 1),
993 MUX(0, "clk_spdif_mux", spdif_p, 0,
994 32, 13, 2),
995 COMP(0, "clk_spdif_div_c", pll_src_cpll_gpll_p, 0,
996 32, 0, 7, 7, 1),
997
998 /* CRU_CLKSEL_CON33 */
999 MUX(0, "clk_uart_src", pll_src_cpll_gpll_p, 0,
1000 33, 15, 1),
1001 MUX(0, "clk_uart0_src", pll_src_cpll_gpll_upll_p, 0,
1002 33, 12, 2),
1003 MUX(SCLK_UART0, "clk_uart0", uart0_p, 0,
1004 33, 8, 2),
1005 CDIV(0, "clk_uart0_div_c", "clk_uart0_src", 0,
1006 33, 0, 7),
1007
1008 /* CRU_CLKSEL_CON34 */
1009 MUX(SCLK_UART1, "clk_uart1", uart1_p, 0,
1010 34, 8, 2),
1011 CDIV(0, "clk_uart1_div_c", "clk_uart_src", 0,
1012 34, 0, 7),
1013
1014 /* CRU_CLKSEL_CON35 */
1015 MUX(SCLK_UART2, "clk_uart2", uart2_p, 0,
1016 35, 8, 2),
1017 CDIV(0, "clk_uart2_div_c", "clk_uart_src", 0,
1018 35, 0, 7),
1019
1020 /* CRU_CLKSEL_CON36 */
1021 MUX(SCLK_UART3, "clk_uart3", uart3_p, 0,
1022 36, 8, 2),
1023 CDIV(0, "clk_uart3_div_c", "clk_uart_src", 0,
1024 36, 0, 7),
1025
1026 /* CRU_CLKSEL_CON37 */
1027 /* unused */
1028
1029 /* CRU_CLKSEL_CON38 */
1030 MUX(0, "clk_testout2_pll_src", pll_src_cpll_gpll_npll_npll_p, 0,
1031 38, 14, 2),
1032 COMP(0, "clk_testout2_c", clk_testout2_p, 0,
1033 38, 8, 5, 13, 1),
1034 MUX(0, "clk_testout1_pll_src", pll_src_cpll_gpll_npll_npll_p, 0,
1035 38, 6, 2),
1036 COMP(0, "clk_testout1_c", clk_testout1_p, 0,
1037 38, 0, 5, 5, 1),
1038
1039 /* CRU_CLKSEL_CON39 */
1040 COMP(0, "aclk_usb3_c", pll_src_cpll_gpll_npll_npll_p, 0,
1041 39, 0, 5, 6, 2),
1042
1043 /* CRU_CLKSEL_CON40 */
1044 COMP(0, "clk_usb3otg0_suspend_c", pll_src_p, 0,
1045 40, 0, 10, 15, 1),
1046
1047 /* CRU_CLKSEL_CON41 */
1048 COMP(0, "clk_usb3otg1_suspend_c", pll_src_p, 0,
1049 41, 0, 10, 15, 1),
1050
1051 /* CRU_CLKSEL_CON42 */
1052 COMP(0, "aclk_hdcp_c", pll_src_cpll_gpll_ppll_p, 0,
1053 42, 8, 5, 14, 2),
1054 COMP(0, "aclk_vio_c", pll_src_cpll_gpll_ppll_p, 0,
1055 42, 0, 5, 6, 2),
1056
1057 /* CRU_CLKSEL_CON43 */
1058 CDIV(0, "pclk_hdcp_c", "aclk_hdcp", 0,
1059 43, 10, 5),
1060 CDIV(0, "hclk_hdcp_c", "aclk_hdcp", 0,
1061 43, 5, 5),
1062 CDIV(0, "pclk_vio_c", "aclk_vio", 0,
1063 43, 0, 5),
1064
1065 /* CRU_CLKSEL_CON44 */
1066 COMP(0, "pclk_edp_c", pll_src_cpll_gpll_p, 0,
1067 44, 8, 6, 15, 1),
1068
1069 /* CRU_CLKSEL_CON45 - XXX clocks in mux are reversed in TRM !!!*/
1070 COMP(0, "clk_hdmi_cec_c", pll_src_p, 0,
1071 45, 0, 10, 15, 1),
1072
1073 /* CRU_CLKSEL_CON46 */
1074 COMP(0, "clk_dp_core_c", pll_src_npll_cpll_gpll_p, 0,
1075 46, 0, 5, 6, 2),
1076
1077 /* CRU_CLKSEL_CON47 */
1078 CDIV(0, "hclk_vop0_pre_c", "aclk_vop0_pre_c", 0,
1079 47, 8, 5),
1080 COMP(0, "aclk_vop0_pre_c", pll_src_vpll_cpll_gpll_npll_p, 0,
1081 47, 0, 5, 6, 2),
1082
1083 /* CRU_CLKSEL_CON48 */
1084 CDIV(0, "hclk_vop1_pre_c", "aclk_vop1_pre", 0,
1085 48, 8, 5),
1086 COMP(0, "aclk_vop1_pre_c", pll_src_vpll_cpll_gpll_npll_p, 0,
1087 48, 0, 5, 6, 2),
1088
1089 /* CRU_CLKSEL_CON49 */
1090 MUX(DCLK_VOP0, "dclk_vop0", dclk_vop0_p, 0,
1091 49, 11, 1),
1092 COMP(0, "dclk_vop0_div_c", pll_src_vpll_cpll_gpll_gpll_p, 0,
1093 49, 0, 8, 8, 2),
1094
1095 /* CRU_CLKSEL_CON50 */
1096 MUX(DCLK_VOP1, "dclk_vop1", dclk_vop1_p, 0,
1097 50, 11, 1),
1098 COMP(0, "dclk_vop1_div_c", pll_src_vpll_cpll_gpll_gpll_p, 0,
1099 50, 0, 8, 8, 2),
1100
1101 /* CRU_CLKSEL_CON51 */
1102 COMP(0, "clk_vop0_pwm_c", pll_src_vpll_cpll_gpll_gpll_p, 0,
1103 51, 0, 5, 6, 2),
1104
1105 /* CRU_CLKSEL_CON52 */
1106 COMP(0, "clk_vop1_pwm_c", pll_src_vpll_cpll_gpll_gpll_p, 0,
1107 52, 0, 5, 6, 2),
1108
1109 /* CRU_CLKSEL_CON53 */
1110 CDIV(0, "hclk_isp0_c", "aclk_isp0", 0,
1111 53, 8, 5),
1112 COMP(0, "aclk_isp0_c", pll_src_cpll_gpll_ppll_p, 0,
1113 53, 0, 5, 6, 2),
1114
1115 /* CRU_CLKSEL_CON54 */
1116 CDIV(0, "hclk_isp1_c", "aclk_isp1", 0,
1117 54, 8, 5),
1118 COMP(0, "aclk_isp1_c", pll_src_cpll_gpll_ppll_p, 0,
1119 54, 0, 5, 6, 2),
1120
1121 /* CRU_CLKSEL_CON55 */
1122 COMP(0, "clk_isp1_c", pll_src_cpll_gpll_npll_npll_p, 0,
1123 55, 8, 5, 14, 2),
1124 COMP(0, "clk_isp0_c", pll_src_cpll_gpll_npll_npll_p, 0,
1125 55, 0, 5, 6, 2),
1126
1127 /* CRU_CLKSEL_CON56 */
1128 COMP(0, "aclk_gic_pre_c", pll_src_cpll_gpll_p, 0,
1129 56, 8, 5, 15, 1),
1130 MUX(0, "clk_cifout_src_c", pll_src_cpll_gpll_npll_npll_p, 0,
1131 56, 6, 2),
1132 COMP(SCLK_CIF_OUT, "clk_cifout", clk_cif_p, 0,
1133 56, 0, 5, 5, 1),
1134
1135 /* CRU_CLKSEL_CON57 */
1136 CDIV(0, "clk_test_24m", "xin24m", 0,
1137 57, 6, 10),
1138 CDIV(PCLK_ALIVE, "pclk_alive", "gpll", 0,
1139 57, 0, 5),
1140
1141 /* CRU_CLKSEL_CON58 */
1142 COMP(0, "clk_spi5_c", pll_src_cpll_gpll_p, 0,
1143 58, 8, 7, 15, 1),
1144 MUX(0, "clk_test_pre", pll_src_cpll_gpll_p, 0,
1145 58, 7, 1),
1146 CDIV(0, "clk_test_c", "clk_test_pre", 0,
1147 58, 0, 5),
1148
1149 /* CRU_CLKSEL_CON59 */
1150 COMP(0, "clk_spi1_c", pll_src_cpll_gpll_p, 0,
1151 59, 8, 7, 15, 1),
1152 COMP(0, "clk_spi0_c", pll_src_cpll_gpll_p, 0,
1153 59, 0, 7, 7, 1),
1154
1155 /* CRU_CLKSEL_CON60 */
1156 COMP(0, "clk_spi4_c", pll_src_cpll_gpll_p, 0,
1157 60, 8, 7, 15, 1),
1158 COMP(0, "clk_spi2_c", pll_src_cpll_gpll_p, 0,
1159 60, 0, 7, 7, 1),
1160
1161 /* CRU_CLKSEL_CON61 */
1162 COMP(0, "clk_i2c5_c", pll_src_cpll_gpll_p, 0,
1163 61, 8, 7, 15, 1),
1164 COMP(0, "clk_i2c1_c", pll_src_cpll_gpll_p, 0,
1165 61, 0, 7, 7, 1),
1166
1167 /* CRU_CLKSEL_CON62 */
1168 COMP(0, "clk_i2c6_c", pll_src_cpll_gpll_p, 0,
1169 62, 8, 7, 15, 1),
1170 COMP(0, "clk_i2c2_c", pll_src_cpll_gpll_p, 0,
1171 62, 0, 7, 7, 1),
1172
1173 /* CRU_CLKSEL_CON63 */
1174 COMP(0, "clk_i2c7_c", pll_src_cpll_gpll_p, 0,
1175 63, 8, 7, 15, 1),
1176 COMP(0, "clk_i2c3_c", pll_src_cpll_gpll_p, 0,
1177 63, 0, 7, 7, 1),
1178
1179 /* CRU_CLKSEL_CON64 */
1180 COMP(0, "clk_uphy0_tcpdphy_ref_c", pll_src_p, 0,
1181 64, 8, 5, 15, 1),
1182 COMP(0, "clk_uphy0_tcpdcore_c", pll_src_24m_32k_cpll_gpll_p, 0,
1183 64, 0, 5, 6, 2),
1184
1185 /* CRU_CLKSEL_CON65 */
1186 COMP(0, "clk_uphy1_tcpdphy_ref_c", pll_src_p, 0,
1187 65, 8, 5, 15, 1),
1188 COMP(0, "clk_uphy1_tcpdcore_c", pll_src_24m_32k_cpll_gpll_p, 0,
1189 65, 0, 5, 6, 2),
1190
1191 /* CRU_CLKSEL_CON99 - 107 */
1192 FRACT(0, "clk_spdif_frac_c", "clk_spdif_div", 0,
1193 99),
1194 FRACT(0, "clk_i2s0_frac_c", "clk_i2s0_div", 0,
1195 96),
1196 FRACT(0, "clk_i2s1_frac_c", "clk_i2s1_div", 0,
1197 97),
1198 FRACT(0, "clk_i2s2_frac_c", "clk_i2s2_div", 0,
1199 98),
1200 FRACT(0, "clk_uart0_frac_c", "clk_uart0_div", 0,
1201 100),
1202 FRACT(0, "clk_uart1_frac_c", "clk_uart1_div", 0,
1203 101),
1204 FRACT(0, "clk_uart2_frac_c", "clk_uart2_div", 0,
1205 102),
1206 FRACT(0, "clk_uart3_frac_c", "clk_uart3_div", 0,
1207 103),
1208 FRACT(0, "clk_test_frac_c", "clk_test_pre", 0,
1209 105),
1210 FRACT(DCLK_VOP0_FRAC, "dclk_vop0_frac", "dclk_vop0_div", 0,
1211 106),
1212 FRACT(DCLK_VOP1_FRAC, "dclk_vop1_frac", "dclk_vop1_div", 0,
1213 107),
1214
1215 /*
1216 * This clock is controlled in the secure world
1217 */
1218 FFACT(PCLK_WDT, "pclk_wdt", "pclk_alive", 1, 1),
1219
1220 /* Not yet implemented yet
1221 * MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "clk_sdmmc", RK3399_SDMMC_CON0, 1),
1222 * MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "clk_sdmmc", RK3399_SDMMC_CON1, 1),
1223 * MMC(SCLK_SDIO_DRV, "sdio_drv", "clk_sdio", RK3399_SDIO_CON0, 1),
1224 * MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "clk_sdio", RK3399_SDIO_CON1, 1),
1225 */
1226
1227 };
1228
1229 static int
rk3399_cru_probe(device_t dev)1230 rk3399_cru_probe(device_t dev)
1231 {
1232
1233 if (!ofw_bus_status_okay(dev))
1234 return (ENXIO);
1235
1236 if (ofw_bus_is_compatible(dev, "rockchip,rk3399-cru")) {
1237 device_set_desc(dev, "Rockchip RK3399 Clock and Reset Unit");
1238 return (BUS_PROBE_DEFAULT);
1239 }
1240
1241 return (ENXIO);
1242 }
1243
1244 static int
rk3399_cru_attach(device_t dev)1245 rk3399_cru_attach(device_t dev)
1246 {
1247 struct rk_cru_softc *sc;
1248
1249 sc = device_get_softc(dev);
1250 sc->dev = dev;
1251
1252 sc->gates = rk3399_gates;
1253 sc->ngates = nitems(rk3399_gates);
1254
1255 sc->clks = rk3399_clks;
1256 sc->nclks = nitems(rk3399_clks);
1257
1258 sc->reset_offset = 0x400;
1259 sc->reset_num = 335;
1260
1261 return (rk_cru_attach(dev));
1262 }
1263
1264 static device_method_t rk3399_cru_methods[] = {
1265 /* Device interface */
1266 DEVMETHOD(device_probe, rk3399_cru_probe),
1267 DEVMETHOD(device_attach, rk3399_cru_attach),
1268
1269 DEVMETHOD_END
1270 };
1271
1272 static devclass_t rk3399_cru_devclass;
1273
1274 DEFINE_CLASS_1(rk3399_cru, rk3399_cru_driver, rk3399_cru_methods,
1275 sizeof(struct rk_cru_softc), rk_cru_driver);
1276
1277 EARLY_DRIVER_MODULE(rk3399_cru, simplebus, rk3399_cru_driver,
1278 rk3399_cru_devclass, 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE);
1279