1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2018 Emmanuel Vadot <[email protected]>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 *
28 * $FreeBSD$
29 */
30
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
33
34 #include <sys/param.h>
35 #include <sys/systm.h>
36 #include <sys/bus.h>
37 #include <sys/rman.h>
38 #include <sys/kernel.h>
39 #include <sys/module.h>
40 #include <machine/bus.h>
41
42 #include <dev/fdt/simplebus.h>
43
44 #include <dev/ofw/ofw_bus.h>
45 #include <dev/ofw/ofw_bus_subr.h>
46
47 #include <dev/extres/clk/clk.h>
48 #include <dev/extres/clk/clk_div.h>
49 #include <dev/extres/clk/clk_fixed.h>
50 #include <dev/extres/clk/clk_mux.h>
51
52 #include <arm64/rockchip/clk/rk_cru.h>
53
54 #include <dt-bindings/clock/rk3288-cru.h>
55
56 #define CRU_SOFTRST_SIZE 12
57
58 #define CRU_APLL_CON(x) (0x000 + (x) * 0x4)
59 #define CRU_DPLL_CON(x) (0x010 + (x) * 0x4)
60 #define CRU_CPLL_CON(x) (0x020 + (x) * 0x4)
61 #define CRU_GPLL_CON(x) (0x030 + (x) * 0x4)
62 #define CRU_NPLL_CON(x) (0x040 + (x) * 0x4)
63 #define CRU_MODE_CON 0x050
64 #define CRU_CLKSEL_CON(x) (0x060 + (x) * 0x4)
65 #define CRU_CLKGATE_CON(x) (0x160 + (x) * 0x4)
66 #define CRU_GLB_SRST_FST_VALUE 0x1b0
67 #define CRU_GLB_SRST_SND_VALUE 0x1b4
68 #define CRU_SOFTRST_CON(x) (0x1b8 + (x) * 0x4)
69 #define CRU_MISC_CON 0x1e8
70 #define CRU_GLB_CNT_TH 0x1ec
71 #define CRU_GLB_RST_CON 0x1f0
72 #define CRU_GLB_RST_ST 0x1f8
73 #define CRU_SDMMC_CON0 0x200
74 #define CRU_SDMMC_CON1 0x204
75 #define CRU_SDIO0_CON0 0x208
76 #define CRU_SDIO0_CON1 0x20c
77 #define CRU_SDIO1_CON0 0x210
78 #define CRU_SDIO1_CON1 0x214
79 #define CRU_EMMC_CON0 0x218
80 #define CRU_EMMC_CON1 0x21c
81
82 /* GATES */
83 #define GATE(_idx, _clkname, _pname, _o, _s) \
84 { \
85 .id = _idx, \
86 .name = _clkname, \
87 .parent_name = _pname, \
88 .offset = CRU_CLKGATE_CON(_o), \
89 .shift = _s, \
90 }
91
92 static struct rk_cru_gate rk3288_gates[] = {
93 /* CRU_CLKGATE_CON0 */
94 GATE(0, "sclk_acc_efuse", "xin24m", 0, 12),
95 GATE(0, "cpll_aclk_cpu", "cpll", 0, 11),
96 GATE(0, "gpll_aclk_cpu", "gpll", 0, 10),
97 GATE(0, "gpll_ddr", "gpll", 0, 9),
98 GATE(0, "dpll_ddr", "dpll", 0, 8),
99 GATE(0, "aclk_bus_2pmu", "aclk_cpu_pre", 0, 7),
100 GATE(PCLK_CPU, "pclk_cpu", "pclk_cpu_s", 0, 5),
101 GATE(HCLK_CPU, "hclk_cpu", "hclk_cpu_s", 0, 4),
102 GATE(ACLK_CPU, "aclk_cpu", "aclk_cpu_pre", 0, 3),
103 GATE(0, "gpll_core", "gpll", 0, 2),
104 GATE(0, "apll_core", "apll", 0, 1),
105
106
107 /* CRU_CLKGATE_CON1 */
108 GATE(0, "uart3_frac", "uart3_frac_s", 1, 15),
109 GATE(0, "uart3_src", "uart3_src_s", 1, 14),
110 GATE(0, "uart2_frac", "uart2_frac_s", 1, 13),
111 GATE(0, "uart2_src", "uart2_src_s", 1, 12),
112 GATE(0, "uart1_frac", "uart1_frac_s", 1, 11),
113 GATE(0, "uart1_src", "uart1_src_s", 1, 10),
114 GATE(0, "uart0_frac", "uart0_frac_s", 1, 9),
115 GATE(0, "uart0_src", "uart0_src_s", 1, 8),
116 GATE(SCLK_TIMER5, "sclk_timer5", "xin24m", 1, 5),
117 GATE(SCLK_TIMER4, "sclk_timer4", "xin24m", 1, 4),
118 GATE(SCLK_TIMER3, "sclk_timer3", "xin24m", 1, 3),
119 GATE(SCLK_TIMER2, "sclk_timer2", "xin24m", 1, 2),
120 GATE(SCLK_TIMER1, "sclk_timer1", "xin24m", 1, 1),
121 GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 1, 0),
122
123 /* CRU_CLKGATE_CON2 */
124 GATE(0, "uart4_frac", "uart4_frac_s", 2, 13),
125 GATE(0, "uart4_src", "uart4_src_s", 2, 12),
126 GATE(SCLK_SPI2, "sclk_spi2", "sclk_spi2_s", 2, 11),
127 GATE(SCLK_SPI1, "sclk_spi1", "sclk_spi1_s", 2, 10),
128 GATE(SCLK_SPI0, "sclk_spi0", "sclk_spi0_s", 2, 9),
129 GATE(SCLK_SARADC, "sclk_saradc", "sclk_saradc_s", 2, 8),
130 GATE(SCLK_TSADC, "sclk_tsadc", "sclk_tsadc_s", 2, 7),
131 GATE(0, "hsadc_src", "hsadc_src_s", 2, 6),
132 GATE(0, "mac_pll_src", "mac_pll_src_s", 2, 5),
133 GATE(PCLK_PERI, "pclk_peri", "pclk_peri_s", 2, 3),
134 GATE(HCLK_PERI, "hclk_peri", "hclk_peri_s", 2, 2),
135 GATE(ACLK_PERI, "aclk_peri", "aclk_peri_src", 2, 1),
136 GATE(0, "aclk_peri_src", "aclk_peri_src_s", 2, 0),
137
138 /* CRU_CLKGATE_CON3 */
139 GATE(SCLK_ISP_JPE, "sclk_isp_jpe", "sclk_isp_jpe_s", 3, 15),
140 GATE(SCLK_ISP, "sclk_isp", "sclk_isp_s", 3, 14),
141 GATE(SCLK_EDP, "sclk_edp", "sclk_edp_s", 3, 13),
142 GATE(SCLK_EDP_24M, "sclk_edp_24m", "sclk_edp_24m_s", 3, 12),
143 GATE(0, "aclk_vdpu", "aclk_vdpu_s", 3, 11),
144 GATE(0, "hclk_vcodec_pre", "hclk_vcodec_pre_s", 3, 10),
145 GATE(0, "aclk_vepu", "aclk_vepu_s", 3, 9),
146 GATE(0, "vip_src", "vip_src_s", 3, 7),
147 /* 6 - Not in TRM, sclk_hsicphy480m in Linux */
148 GATE(0, "aclk_rga_pre", "aclk_rga_pre_s", 3, 5),
149 GATE(SCLK_RGA, "sclk_rga", "sclk_rga_s", 3, 4),
150 GATE(DCLK_VOP1, "dclk_vop1", "dclk_vop1_s", 3, 3),
151 GATE(0, "aclk_vio1", "aclk_vio1_s", 3, 2),
152 GATE(DCLK_VOP0, "dclk_vop0", "dclk_vop0_s", 3, 1),
153 GATE(0, "aclk_vio0", "aclk_vio0_s", 3, 0),
154
155 /* CRU_CLKGATE_CON4 */
156 /* 15 - Test clock generator */
157 GATE(0, "jtag", "ext_jtag", 4, 14),
158 GATE(0, "sclk_ddrphy1", "ddrphy", 4, 13),
159 GATE(0, "sclk_ddrphy0", "ddrphy", 4, 12),
160 GATE(0, "sclk_tspout", "sclk_tspout_s", 4, 11),
161 GATE(0, "sclk_tsp", "sclk_tsp_s", 4, 10),
162 GATE(SCLK_SPDIF8CH, "sclk_spdif_8ch", "spdif_8ch_mux", 4, 9),
163 GATE(0, "spdif_8ch_frac", "spdif_8ch_frac_s", 4, 8),
164 GATE(0, "spdif_8ch_pre", "spdif_8ch_pre_s", 4, 7),
165 GATE(SCLK_SPDIF, "sclk_spdif", "spdif_mux", 4, 6),
166 GATE(0, "spdif_frac", "spdif_frac_s", 4, 5),
167 GATE(0, "spdif_pre", "spdif_pre_s", 4, 4),
168 GATE(SCLK_I2S0, "sclk_i2s0", "i2s_pre", 4, 3),
169 GATE(0, "i2s_frac", "i2s_frac_s", 4, 2),
170 GATE(0, "i2s_src", "i2s_src_s", 4, 1),
171 GATE(SCLK_I2S0_OUT, "i2s0_clkout", "i2s0_clkout_s", 4, 1),
172
173 /* CRU_CLKGATE_CON5 */
174 GATE(SCLK_MIPIDSI_24M, "sclk_mipidsi_24m", "xin24m", 5, 15),
175 GATE(SCLK_USBPHY480M_SRC, "usbphy480m_src", "usbphy480m_src_s", 5, 14),
176 GATE(SCLK_PS2C, "sclk_ps2c", "xin24m", 5, 13),
177 GATE(SCLK_HDMI_HDCP, "sclk_hdmi_hdcp", "xin24m", 5, 12),
178 GATE(SCLK_HDMI_CEC, "sclk_hdmi_cec", "xin32k", 5, 11),
179 GATE(SCLK_PVTM_GPU, "sclk_pvtm_gpu", "xin24m", 5, 10),
180 GATE(SCLK_PVTM_CORE, "sclk_pvtm_core", "xin24m", 5, 9),
181 GATE(0, "pclk_pd_pmu", "pclk_pd_pmu_s", 5, 8),
182 GATE(SCLK_GPU, "sclk_gpu", "sclk_gpu_s", 5, 7),
183 GATE(SCLK_NANDC1, "sclk_nandc1", "sclk_nandc1_s", 5, 6),
184 GATE(SCLK_NANDC0, "sclk_nandc0", "sclk_nandc0_s", 5, 5),
185 GATE(SCLK_CRYPTO, "crypto", "crypto_s", 5, 4),
186 GATE(SCLK_MACREF_OUT, "sclk_macref_out", "mac_clk", 5, 3),
187 GATE(SCLK_MACREF, "sclk_macref", "mac_clk", 5, 2),
188 GATE(SCLK_MAC_TX, "sclk_mac_tx", "mac_clk", 5, 1),
189 GATE(SCLK_MAC_RX, "sclk_mac_rx", "mac_clk", 5, 0),
190
191
192 /* CRU_CLKGATE_CON6 */
193 GATE(PCLK_I2C4, "pclk_i2c4", "pclk_peri", 6, 15),
194 GATE(PCLK_I2C3, "pclk_i2c3", "pclk_peri", 6, 14),
195 GATE(PCLK_I2C1, "pclk_i2c1", "pclk_peri", 6, 13),
196 GATE(PCLK_UART4, "pclk_uart4", "pclk_peri", 6, 12),
197 GATE(PCLK_UART3, "pclk_uart3", "pclk_peri", 6, 11),
198 GATE(PCLK_UART1, "pclk_uart1", "pclk_peri", 6, 9),
199 GATE(PCLK_UART0, "pclk_uart0", "pclk_peri", 6, 8),
200 GATE(PCLK_PS2C, "pclk_ps2c", "pclk_peri", 6, 7),
201 GATE(PCLK_SPI2, "pclk_spi2", "pclk_peri", 6, 6),
202 GATE(PCLK_SPI1, "pclk_spi1", "pclk_peri", 6, 5),
203 GATE(PCLK_SPI0, "pclk_spi0", "pclk_peri", 6, 4),
204 GATE(ACLK_DMAC2, "aclk_dmac2", "aclk_peri", 6, 3),
205 GATE(0, "aclk_peri_axi_matrix", "aclk_peri", 6, 2),
206 GATE(0, "pclk_peri_matrix", "pclk_peri", 6, 1),
207 GATE(0, "hclk_peri_matrix", "hclk_peri", 6, 0),
208
209
210 /* CRU_CLKGATE_CON7 */
211 GATE(HCLK_NANDC1, "hclk_nandc1", "hclk_peri", 7, 15),
212 GATE(HCLK_NANDC0, "hclk_nandc0", "hclk_peri", 7, 14),
213 GATE(0, "hclk_mem", "hclk_peri", 7, 13),
214 GATE(0, "hclk_emem", "hclk_peri", 7, 12),
215 GATE(0, "aclk_peri_niu", "aclk_peri", 7, 11),
216 GATE(0, "hclk_peri_ahb_arbi", "hclk_peri", 7, 10),
217 GATE(0, "hclk_usb_peri", "hclk_peri", 7, 9),
218 /* 8 - Not in TRM - hclk_hsic in Linux */
219 GATE(HCLK_USBHOST1, "hclk_host1", "hclk_peri", 7, 7),
220 GATE(HCLK_USBHOST0, "hclk_host0", "hclk_peri", 7, 6),
221 GATE(0, "pmu_hclk_otg0", "hclk_peri", 7, 5),
222 GATE(HCLK_OTG0, "hclk_otg0", "hclk_peri", 7, 4),
223 GATE(PCLK_SIM, "pclk_sim", "pclk_peri", 7, 3),
224 GATE(PCLK_TSADC, "pclk_tsadc", "pclk_peri", 7, 2),
225 GATE(PCLK_SARADC, "pclk_saradc", "pclk_peri", 7, 1),
226 GATE(PCLK_I2C5, "pclk_i2c5", "pclk_peri", 7, 0),
227
228 /* CRU_CLKGATE_CON8 */
229 GATE(ACLK_MMU, "aclk_mmu", "aclk_peri", 8, 12),
230 /* 11 - 9 27m_tsp, hsadc_1_tsp, hsadc_1_tsp */
231 GATE(HCLK_TSP, "hclk_tsp", "hclk_peri", 8, 8),
232 GATE(HCLK_HSADC, "hclk_hsadc", "hclk_peri", 8, 7),
233 GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 8, 6),
234 GATE(HCLK_SDIO1, "hclk_sdio1", "hclk_peri", 8, 5),
235 GATE(HCLK_SDIO0, "hclk_sdio0", "hclk_peri", 8, 4),
236 GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 8, 3),
237 GATE(HCLK_GPS, "hclk_gps", "aclk_peri", 8, 2),
238 GATE(PCLK_GMAC, "pclk_gmac", "pclk_peri", 8, 1),
239 GATE(ACLK_GMAC, "aclk_gmac", "aclk_peri", 8, 0),
240
241 /* CRU_CLKGATE_CON9 */
242 GATE(HCLK_VCODEC, "hclk_vcodec", "hclk_vcodec_pre", 9, 1),
243 GATE(ACLK_VCODEC, "aclk_vcodec", "aclk_vcodec_pre", 9, 0),
244
245 /* CRU_CLKGATE_CON10 */
246 GATE(PCLK_PUBL0, "pclk_publ0", "pclk_cpu", 10, 15),
247 GATE(PCLK_DDRUPCTL0, "pclk_ddrupctl0", "pclk_cpu", 10, 14),
248 GATE(0, "aclk_strc_sys", "aclk_cpu", 10, 13),
249 GATE(ACLK_DMAC1, "aclk_dmac1", "aclk_cpu", 10, 12),
250 GATE(HCLK_SPDIF8CH, "hclk_spdif_8ch", "hclk_cpu", 10, 11),
251 GATE(HCLK_SPDIF, "hclk_spdif", "hclk_cpu", 10, 10),
252 GATE(HCLK_ROM, "hclk_rom", "hclk_cpu", 10, 9),
253 GATE(HCLK_I2S0, "hclk_i2s0", "hclk_cpu", 10, 8),
254 GATE(0, "sclk_intmem2", "aclk_cpu", 10, 7),
255 GATE(0, "sclk_intmem1", "aclk_cpu", 10, 6),
256 GATE(0, "sclk_intmem0", "aclk_cpu", 10, 5),
257 GATE(0, "aclk_intmem", "aclk_cpu", 10, 4),
258 GATE(PCLK_I2C2, "pclk_i2c2", "pclk_cpu", 10, 3),
259 GATE(PCLK_I2C0, "pclk_i2c0", "pclk_cpu", 10, 2),
260 GATE(PCLK_TIMER, "pclk_timer", "pclk_cpu", 10, 1),
261 GATE(PCLK_PWM, "pclk_pwm", "pclk_cpu", 10, 0),
262
263 /* CRU_CLKGATE_CON11 */
264 GATE(PCLK_RKPWM, "pclk_rkpwm", "pclk_cpu", 11, 11),
265 GATE(PCLK_EFUSE256, "pclk_efuse_256", "pclk_cpu", 11, 10),
266 GATE(PCLK_UART2, "pclk_uart2", "pclk_cpu", 11, 9),
267 GATE(0, "aclk_ccp", "aclk_cpu", 11, 8),
268 GATE(HCLK_CRYPTO, "hclk_crypto", "hclk_cpu", 11, 7),
269 GATE(ACLK_CRYPTO, "aclk_crypto", "aclk_cpu", 11, 6),
270 GATE(0, "nclk_ddrupctl1", "ddrphy", 11, 5),
271 GATE(0, "nclk_ddrupctl0", "ddrphy", 11, 4),
272 GATE(PCLK_TZPC, "pclk_tzpc", "pclk_cpu", 11, 3),
273 GATE(PCLK_EFUSE1024, "pclk_efuse_1024", "pclk_cpu", 11, 2),
274 GATE(PCLK_PUBL1, "pclk_publ1", "pclk_cpu", 11, 1),
275 GATE(PCLK_DDRUPCTL1, "pclk_ddrupctl1", "pclk_cpu", 11, 0),
276
277 /* CRU_CLKGATE_CON12 */
278 GATE(0, "pclk_core_niu", "pclk_dbg_pre", 12, 11),
279 GATE(0, "cs_dbg", "pclk_dbg_pre", 12, 10),
280 GATE(0, "pclk_dbg", "pclk_dbg_pre", 12, 9),
281 GATE(0, "armcore0", "armcore0_s", 12, 8),
282 GATE(0, "armcore1", "armcore1_s", 12, 7),
283 GATE(0, "armcore2", "armcore2_s", 12, 6),
284 GATE(0, "armcore3", "armcore3_s", 12, 5),
285 GATE(0, "l2ram", "l2ram_s", 12, 4),
286 GATE(0, "aclk_core_m0", "aclk_core_m0_s", 12, 3),
287 GATE(0, "aclk_core_mp", "aclk_core_mp_s", 12, 2),
288 GATE(0, "atclk", "atclk_s", 12, 1),
289 GATE(0, "pclk_dbg_pre", "pclk_dbg_pre_s", 12, 0),
290
291 /* CRU_CLKGATE_CON13 */
292 GATE(SCLK_HEVC_CORE, "sclk_hevc_core", "sclk_hevc_core_s", 13, 15),
293 GATE(SCLK_HEVC_CABAC, "sclk_hevc_cabac", "sclk_hevc_cabac_s", 13, 14),
294 GATE(ACLK_HEVC, "aclk_hevc", "aclk_hevc_s", 13, 13),
295 GATE(0, "wii", "wifi_frac_s", 13, 12),
296 GATE(SCLK_LCDC_PWM1, "sclk_lcdc_pwm1", "xin24m", 13, 11),
297 GATE(SCLK_LCDC_PWM0, "sclk_lcdc_pwm0", "xin24m", 13, 10),
298 /* 9 - Not in TRM - hsicphy12m_xin12m in Linux */
299 GATE(0, "c2c_host", "aclk_cpu_src", 13, 8),
300 GATE(SCLK_OTG_ADP, "sclk_otg_adp", "xin32k", 13, 7),
301 GATE(SCLK_OTGPHY2, "sclk_otgphy2", "xin24m", 13, 6),
302 GATE(SCLK_OTGPHY1, "sclk_otgphy1", "xin24m", 13, 5),
303 GATE(SCLK_OTGPHY0, "sclk_otgphy0", "xin24m", 13, 4),
304 GATE(SCLK_EMMC, "sclk_emmc", "sclk_emmc_s", 13, 3),
305 GATE(SCLK_SDIO1, "sclk_sdio1", "sclk_sdio1_s", 13, 2),
306 GATE(SCLK_SDIO0, "sclk_sdio0", "sclk_sdio0_s", 13, 1),
307 GATE(SCLK_SDMMC, "sclk_sdmmc", "sclk_sdmmc_s", 13, 0),
308
309 /* CRU_CLKGATE_CON14 */
310 GATE(0, "pclk_alive_niu", "pclk_pd_alive", 14, 12),
311 GATE(PCLK_GRF, "pclk_grf", "pclk_pd_alive", 14, 11),
312 GATE(PCLK_GPIO8, "pclk_gpio8", "pclk_pd_alive", 14, 8),
313 GATE(PCLK_GPIO7, "pclk_gpio7", "pclk_pd_alive", 14, 7),
314 GATE(PCLK_GPIO6, "pclk_gpio6", "pclk_pd_alive", 14, 6),
315 GATE(PCLK_GPIO5, "pclk_gpio5", "pclk_pd_alive", 14, 5),
316 GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_pd_alive", 14, 4),
317 GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_pd_alive", 14, 3),
318 GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_pd_alive", 14, 2),
319 GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_pd_alive", 14, 1),
320
321 /* CRU_CLKGATE_CON15*/
322 GATE(HCLK_VIP, "hclk_vip", "hclk_vio", 15, 15),
323 GATE(ACLK_VIP, "aclk_vip", "aclk_vio0", 15, 14),
324 GATE(ACLK_RGA_NIU, "aclk_rga_niu", "aclk_rga_pre", 15, 13),
325 GATE(ACLK_VIO1_NIU, "aclk_vio1_niu", "aclk_vio1", 15, 12),
326 GATE(ACLK_VIO0_NIU, "aclk_vio0_niu", "aclk_vio0", 15, 11),
327 GATE(HCLK_VIO_NIU, "hclk_vio_niu", "hclk_vio", 15, 10),
328 GATE(HCLK_VIO_AHB_ARBI, "hclk_vio_ahb_arbi", "hclk_vio",15, 9),
329 GATE(HCLK_VOP1, "hclk_vop1", "hclk_vio", 15, 8),
330 GATE(ACLK_VOP1, "aclk_vop1", "aclk_vio1", 15, 7),
331 GATE(HCLK_VOP0, "hclk_vop0", "hclk_vio", 15, 6),
332 GATE(ACLK_VOP0, "aclk_vop0", "aclk_vio0", 15, 5),
333 /* 4 - aclk_lcdc_iep */
334 GATE(HCLK_IEP, "hclk_iep", "hclk_vio", 15, 3),
335 GATE(ACLK_IEP, "aclk_iep", "aclk_vio0", 15, 2),
336 GATE(HCLK_RGA, "hclk_rga", "hclk_vio", 15, 1),
337 GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 15, 0),
338
339 /* CRU_CLKGATE_CON16 */
340 GATE(PCLK_VIO2_H2P, "pclk_vio2_h2p", "hclk_vio", 16, 11),
341 GATE(HCLK_VIO2_H2P, "hclk_vio2_h2p", "hclk_vio", 16, 10),
342 GATE(PCLK_HDMI_CTRL, "pclk_hdmi_ctrl", "hclk_vio", 16, 9),
343 GATE(PCLK_EDP_CTRL, "pclk_edp_ctrl", "hclk_vio", 16, 8),
344 GATE(PCLK_LVDS_PHY, "pclk_lvds_phy", "hclk_vio", 16, 7),
345 GATE(PCLK_MIPI_CSI, "pclk_mipi_csi", "hclk_vio", 16, 6),
346 GATE(PCLK_MIPI_DSI1, "pclk_mipi_dsi1", "hclk_vio", 16, 5),
347 GATE(PCLK_MIPI_DSI0, "pclk_mipi_dsi0", "hclk_vio", 16, 4),
348 GATE(PCLK_ISP_IN, "pclk_isp_in", "ext_isp", 16, 3),
349 GATE(ACLK_ISP, "aclk_isp", "aclk_vio1", 16, 2),
350 GATE(HCLK_ISP, "hclk_isp", "hclk_vio", 16, 1),
351 GATE(0, "pclk_vip_in", "ext_vip", 16, 0),
352
353 /* CRU_CLKGATE_CON17 */
354 GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pd_pmu", 17, 4),
355 GATE(PCLK_SGRF, "pclk_sgrf", "pclk_pd_pmu", 17, 3),
356 GATE(0, "pclk_pmu_niu", "pclk_pd_pmu", 17, 2),
357 GATE(0, "pclk_intmem1", "pclk_pd_pmu", 17, 1),
358 GATE(PCLK_PMU, "pclk_pmu", "pclk_pd_pmu", 17, 0),
359
360 /* CRU_CLKGATE_CON18 */
361 GATE(ACLK_GPU, "aclk_gpu", "sclk_gpu", 18, 0),
362 };
363
364 /*
365 * PLLs
366 */
367 #define PLL_RATE_BA(_hz, _ref, _fb, _post, _ba) \
368 { \
369 .freq = _hz, \
370 .refdiv = _ref, \
371 .fbdiv = _fb, \
372 .postdiv1 = _post, \
373 .bwadj = _ba, \
374 }
375
376 #define PLL_RATE(_mhz, _ref, _fb, _post) \
377 PLL_RATE_BA(_mhz, _ref, _fb, _post, ((_fb < 2) ? 1 : _fb >> 1))
378
379 static struct rk_clk_pll_rate rk3288_pll_rates[] = {
380 PLL_RATE( 2208000000, 1, 92, 1),
381 PLL_RATE( 2184000000, 1, 91, 1),
382 PLL_RATE( 2160000000, 1, 90, 1),
383 PLL_RATE( 2136000000, 1, 89, 1),
384 PLL_RATE( 2112000000, 1, 88, 1),
385 PLL_RATE( 2088000000, 1, 87, 1),
386 PLL_RATE( 2064000000, 1, 86, 1),
387 PLL_RATE( 2040000000, 1, 85, 1),
388 PLL_RATE( 2016000000, 1, 84, 1),
389 PLL_RATE( 1992000000, 1, 83, 1),
390 PLL_RATE( 1968000000, 1, 82, 1),
391 PLL_RATE( 1944000000, 1, 81, 1),
392 PLL_RATE( 1920000000, 1, 80, 1),
393 PLL_RATE( 1896000000, 1, 79, 1),
394 PLL_RATE( 1872000000, 1, 78, 1),
395 PLL_RATE( 1848000000, 1, 77, 1),
396 PLL_RATE( 1824000000, 1, 76, 1),
397 PLL_RATE( 1800000000, 1, 75, 1),
398 PLL_RATE( 1776000000, 1, 74, 1),
399 PLL_RATE( 1752000000, 1, 73, 1),
400 PLL_RATE( 1728000000, 1, 72, 1),
401 PLL_RATE( 1704000000, 1, 71, 1),
402 PLL_RATE( 1680000000, 1, 70, 1),
403 PLL_RATE( 1656000000, 1, 69, 1),
404 PLL_RATE( 1632000000, 1, 68, 1),
405 PLL_RATE( 1608000000, 1, 67, 1),
406 PLL_RATE( 1560000000, 1, 65, 1),
407 PLL_RATE( 1512000000, 1, 63, 1),
408 PLL_RATE( 1488000000, 1, 62, 1),
409 PLL_RATE( 1464000000, 1, 61, 1),
410 PLL_RATE( 1440000000, 1, 60, 1),
411 PLL_RATE( 1416000000, 1, 59, 1),
412 PLL_RATE( 1392000000, 1, 58, 1),
413 PLL_RATE( 1368000000, 1, 57, 1),
414 PLL_RATE( 1344000000, 1, 56, 1),
415 PLL_RATE( 1320000000, 1, 55, 1),
416 PLL_RATE( 1296000000, 1, 54, 1),
417 PLL_RATE( 1272000000, 1, 53, 1),
418 PLL_RATE( 1248000000, 1, 52, 1),
419 PLL_RATE( 1224000000, 1, 51, 1),
420 PLL_RATE( 1200000000, 1, 50, 1),
421 PLL_RATE( 1188000000, 2, 99, 1),
422 PLL_RATE( 1176000000, 1, 49, 1),
423 PLL_RATE( 1128000000, 1, 47, 1),
424 PLL_RATE( 1104000000, 1, 46, 1),
425 PLL_RATE( 1008000000, 1, 84, 2),
426 PLL_RATE( 912000000, 1, 76, 2),
427 PLL_RATE( 891000000, 8, 594, 2),
428 PLL_RATE( 888000000, 1, 74, 2),
429 PLL_RATE( 816000000, 1, 68, 2),
430 PLL_RATE( 798000000, 2, 133, 2),
431 PLL_RATE( 792000000, 1, 66, 2),
432 PLL_RATE( 768000000, 1, 64, 2),
433 PLL_RATE( 742500000, 8, 495, 2),
434 PLL_RATE( 696000000, 1, 58, 2),
435 PLL_RATE_BA( 621000000, 1, 207, 8, 1),
436 PLL_RATE( 600000000, 1, 50, 2),
437 PLL_RATE_BA( 594000000, 1, 198, 8, 1),
438 PLL_RATE( 552000000, 1, 46, 2),
439 PLL_RATE( 504000000, 1, 84, 4),
440 PLL_RATE( 500000000, 3, 125, 2),
441 PLL_RATE( 456000000, 1, 76, 4),
442 PLL_RATE( 428000000, 1, 107, 6),
443 PLL_RATE( 408000000, 1, 68, 4),
444 PLL_RATE( 400000000, 3, 100, 2),
445 PLL_RATE_BA( 394000000, 1, 197, 12, 1),
446 PLL_RATE( 384000000, 2, 128, 4),
447 PLL_RATE( 360000000, 1, 60, 4),
448 PLL_RATE_BA( 356000000, 1, 178, 12, 1),
449 PLL_RATE_BA( 324000000, 1, 189, 14, 1),
450 PLL_RATE( 312000000, 1, 52, 4),
451 PLL_RATE_BA( 308000000, 1, 154, 12, 1),
452 PLL_RATE_BA( 303000000, 1, 202, 16, 1),
453 PLL_RATE( 300000000, 1, 75, 6),
454 PLL_RATE_BA( 297750000, 2, 397, 16, 1),
455 PLL_RATE_BA( 293250000, 2, 391, 16, 1),
456 PLL_RATE_BA( 292500000, 1, 195, 16, 1),
457 PLL_RATE( 273600000, 1, 114, 10),
458 PLL_RATE_BA( 273000000, 1, 182, 16, 1),
459 PLL_RATE_BA( 270000000, 1, 180, 16, 1),
460 PLL_RATE_BA( 266250000, 2, 355, 16, 1),
461 PLL_RATE_BA( 256500000, 1, 171, 16, 1),
462 PLL_RATE( 252000000, 1, 84, 8),
463 PLL_RATE_BA( 250500000, 1, 167, 16, 1),
464 PLL_RATE_BA( 243428571, 1, 142, 14, 1),
465 PLL_RATE( 238000000, 1, 119, 12),
466 PLL_RATE_BA( 219750000, 2, 293, 16, 1),
467 PLL_RATE_BA( 216000000, 1, 144, 16, 1),
468 PLL_RATE_BA( 213000000, 1, 142, 16, 1),
469 PLL_RATE( 195428571, 1, 114, 14),
470 PLL_RATE( 160000000, 1, 80, 12),
471 PLL_RATE( 157500000, 1, 105, 16),
472 PLL_RATE( 126000000, 1, 84, 16),
473 PLL_RATE( 48000000, 1, 64, 32),
474 {},
475 };
476
477 static struct rk_clk_armclk_rates rk3288_armclk_rates[] = {
478 { 1800000000, 1},
479 { 1704000000, 1},
480 { 1608000000, 1},
481 { 1512000000, 1},
482 { 1416000000, 1},
483 { 1200000000, 1},
484 { 1008000000, 1},
485 { 816000000, 1},
486 { 696000000, 1},
487 { 600000000, 1},
488 { 408000000, 1},
489 { 312000000, 1},
490 { 216000000, 1},
491 { 126000000, 1},
492 };
493
494
495 /* Fixed rate clock. */
496 #define FRATE(_id, _name, _freq) \
497 { \
498 .type = RK_CLK_FIXED, \
499 .clk.fixed = &(struct clk_fixed_def) { \
500 .clkdef.id = _id, \
501 .clkdef.name = _name, \
502 .clkdef.parent_names = NULL, \
503 .clkdef.parent_cnt = 0, \
504 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \
505 .freq = _freq, \
506 }, \
507 }
508
509 /* Fixed rate multipier/divider. */
510 #define FACT(_id, _name, _pname, _mult, _div) \
511 { \
512 .type = RK_CLK_FIXED, \
513 .clk.fixed = &(struct clk_fixed_def) { \
514 .clkdef.id = _id, \
515 .clkdef.name = _name, \
516 .clkdef.parent_names = (const char *[]){_pname}, \
517 .clkdef.parent_cnt = 1, \
518 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \
519 .mult = _mult, \
520 .div = _div, \
521 }, \
522 }
523
524 /* Standard PLL. */
525 #define PLL(_id, _name, _base, _shift) \
526 { \
527 .type = RK3066_CLK_PLL, \
528 .clk.pll = &(struct rk_clk_pll_def) { \
529 .clkdef.id = _id, \
530 .clkdef.name = _name, \
531 .clkdef.parent_names = pll_src_p, \
532 .clkdef.parent_cnt = nitems(pll_src_p), \
533 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \
534 .base_offset = _base, \
535 .mode_reg = CRU_MODE_CON, \
536 .mode_shift = _shift, \
537 .rates = rk3288_pll_rates, \
538 }, \
539 }
540
541 /* Multiplexer. */
542 #define MUX(_id, _name, _pn, _f, _mo, _ms, _mw) \
543 { \
544 .type = RK_CLK_MUX, \
545 .clk.mux = &(struct rk_clk_mux_def) { \
546 .clkdef.id = _id, \
547 .clkdef.name = _name, \
548 .clkdef.parent_names = _pn, \
549 .clkdef.parent_cnt = nitems(_pn), \
550 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \
551 .offset = CRU_CLKSEL_CON(_mo), \
552 .shift = _ms, \
553 .width = _mw, \
554 .mux_flags = _f, \
555 }, \
556 }
557
558 #define ARMDIV(_id, _name, _pn, _r, _o, _ds, _dw, _ms, _mw, _mp, _ap) \
559 { \
560 .type = RK_CLK_ARMCLK, \
561 .clk.armclk = &(struct rk_clk_armclk_def) { \
562 .clkdef.id = _id, \
563 .clkdef.name = _name, \
564 .clkdef.parent_names = _pn, \
565 .clkdef.parent_cnt = nitems(_pn), \
566 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \
567 .muxdiv_offset = CRU_CLKSEL_CON(_o), \
568 .mux_shift = _ms, \
569 .mux_width = _mw, \
570 .div_shift = _ds, \
571 .div_width = _dw, \
572 .main_parent = _mp, \
573 .alt_parent = _ap, \
574 .rates = _r, \
575 .nrates = nitems(_r), \
576 }, \
577 }
578
579 /* Fixed rate multipier/divider. */
580 #define FRACT(_id, _name, _pname, _f, _o) \
581 { \
582 .type = RK_CLK_FRACT, \
583 .clk.fract = &(struct rk_clk_fract_def) { \
584 .clkdef.id = _id, \
585 .clkdef.name = _name, \
586 .clkdef.parent_names = (const char *[]){_pname}, \
587 .clkdef.parent_cnt = 1, \
588 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \
589 .offset = CRU_CLKSEL_CON(_o), \
590 .flags = _f, \
591 }, \
592 }
593
594 /* Full composite clock. */
595 #define COMP(_id, _name, _pnames, _f, _o, _ds, _dw, _ms, _mw) \
596 { \
597 .type = RK_CLK_COMPOSITE, \
598 .clk.composite = &(struct rk_clk_composite_def) { \
599 .clkdef.id = _id, \
600 .clkdef.name = _name, \
601 .clkdef.parent_names = _pnames, \
602 .clkdef.parent_cnt = nitems(_pnames), \
603 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \
604 .muxdiv_offset = CRU_CLKSEL_CON(_o), \
605 .mux_shift = _ms, \
606 .mux_width = _mw, \
607 .div_shift = _ds, \
608 .div_width = _dw, \
609 .flags = RK_CLK_COMPOSITE_HAVE_MUX | _f, \
610 }, \
611 }
612
613 /* Composite clock without mux (divider olnly). */
614 #define CDIV(_id, _name, _pname, _f, _o, _ds, _dw) \
615 { \
616 .type = RK_CLK_COMPOSITE, \
617 .clk.composite = &(struct rk_clk_composite_def) { \
618 .clkdef.id = _id, \
619 .clkdef.name = _name, \
620 .clkdef.parent_names = (const char *[]){_pname}, \
621 .clkdef.parent_cnt = 1, \
622 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \
623 .muxdiv_offset = CRU_CLKSEL_CON(_o), \
624 .div_shift = _ds, \
625 .div_width = _dw, \
626 .flags = _f, \
627 }, \
628 }
629
630
631 #define PLIST(_name) static const char *_name[]
632 PLIST(pll_src_p) = {"xin24m", "xin24m", "xin32k"};
633 PLIST(armclk_p)= {"apll_core", "gpll_core"};
634 PLIST(ddrphy_p) = {"dpll_ddr", "gpll_ddr"};
635 PLIST(aclk_cpu_p) = {"cpll_aclk_cpu", "gpll_aclk_cpu"};
636
637 PLIST(cpll_gpll_p) = {"cpll", "gpll"};
638 PLIST(npll_cpll_gpll_p) = {"npll", "cpll", "gpll"};
639 PLIST(cpll_gpll_npll_p) = {"cpll", "gpll", "npll"};
640 PLIST(cpll_gpll_usb480m_p)= {"cpll", "gpll", "usbphy480m_src"};
641 PLIST(cpll_gpll_usb480m_npll_p) = {"cpll", "gpll", "usbphy480m_src", "npll"};
642
643 PLIST(mmc_p) = {"cpll", "gpll", "xin24m", "xin24m"};
644 PLIST(i2s_pre_p) = {"i2s_src", "i2s_frac", "ext_i2s", "xin12m"};
645 PLIST(i2s_clkout_p) = {"i2s_pre", "xin12m"};
646 PLIST(spdif_p) = {"spdif_pre", "spdif_frac", "xin12m"};
647 PLIST(spdif_8ch_p) = {"spdif_8ch_pre", "spdif_8ch_frac", "xin12m"};
648 PLIST(uart0_p) = {"uart0_src", "uart0_frac", "xin24m"};
649 PLIST(uart1_p) = {"uart1_src", "uart1_frac", "xin24m"};
650 PLIST(uart2_p) = {"uart2_src", "uart2_frac", "xin24m"};
651 PLIST(uart3_p) = {"uart3_src", "uart3_frac", "xin24m"};
652 PLIST(uart4_p) = {"uart4_src", "uart4_frac", "xin24m"};
653 PLIST(vip_out_p) = {"vip_src", "xin24m"};
654 PLIST(mac_p) = {"mac_pll_src", "ext_gmac"};
655 PLIST(hsadcout_p) = {"hsadc_src", "ext_hsadc"};
656 PLIST(edp_24m_p) = {"ext_edp_24m", "xin24m"};
657 PLIST(tspout_p) = {"cpll", "gpll", "npll", "xin27m"};
658 PLIST(wifi_p) = {"cpll", "gpll"};
659 PLIST(usbphy480m_p) = {"sclk_otgphy1_480m", "sclk_otgphy2_480m", "sclk_otgphy0_480m"};
660
661 /* PLIST(aclk_vcodec_pre_p) = {"aclk_vepu", "aclk_vdpu"}; */
662
663
664 static struct rk_clk rk3288_clks[] = {
665 /* External clocks */
666 LINK("xin24m"),
667 FRATE(0, "xin32k", 32000),
668 FRATE(0, "xin27m", 27000000),
669 FRATE(0, "ext_hsadc", 0),
670 FRATE(0, "ext_jtag", 0),
671 FRATE(0, "ext_isp", 0),
672 FRATE(0, "ext_vip", 0),
673 FRATE(0, "ext_i2s", 0),
674 FRATE(0, "ext_edp_24m", 0),
675
676 FRATE(0, "sclk_otgphy0_480m", 0),
677 FRATE(0, "sclk_otgphy1_480m", 0),
678 FRATE(0, "sclk_otgphy2_480m", 0),
679
680 FRATE(0, "aclk_vcodec_pre", 0),
681
682 /* Fixed dividers */
683 FACT(0, "xin12m", "xin24m", 1, 2),
684 FACT(0, "hclk_vcodec_pre_s", "aclk_vcodec_pre", 1, 4),
685
686 PLL(PLL_APLL, "apll", CRU_APLL_CON(0), 0),
687 PLL(PLL_DPLL, "dpll", CRU_DPLL_CON(0), 4),
688 PLL(PLL_CPLL, "cpll", CRU_CPLL_CON(0), 8),
689 PLL(PLL_GPLL, "gpll", CRU_GPLL_CON(0), 12),
690 PLL(PLL_NPLL, "npll", CRU_NPLL_CON(0), 14),
691
692 /* CRU_CLKSEL0_CON */
693 ARMDIV(ARMCLK, "armclk", armclk_p, rk3288_armclk_rates,
694 0, 8, 5, 15, 1, 0, 1),
695 CDIV(0, "aclk_core_mp_s", "armclk", 0,
696 0, 4, 4),
697 CDIV(0, "aclk_core_m0_s", "armclk", 0,
698 0, 0, 4),
699
700 /* CRU_CLKSEL1_CON */
701 CDIV(0, "pclk_cpu_s", "aclk_cpu_pre", 0,
702 1, 12, 3),
703 CDIV(0, "hclk_cpu_s", "aclk_cpu_pre", RK_CLK_COMPOSITE_DIV_EXP,
704 1, 8, 2),
705 COMP(0, "aclk_cpu_src", aclk_cpu_p, 0,
706 1, 3, 5, 15, 1),
707 CDIV(0, "aclk_cpu_pre", "aclk_cpu_src", 0,
708 1, 0, 3),
709
710 /* CRU_CLKSEL2_CON */
711 /* 12:8 testout_div */
712 CDIV(0, "sclk_tsadc_s", "xin32k", 0,
713 2, 0, 6),
714
715 /* CRU_CLKSEL3_CON */
716 MUX(SCLK_UART4, "sclk_uart4", uart4_p, 0,
717 3, 8, 2),
718 CDIV(0, "uart4_src_s", "uart_src", 0,
719 3, 0, 7),
720
721 /* CRU_CLKSEL4_CON */
722 MUX(0, "i2s_pre", i2s_pre_p, 0,
723 4, 8, 2),
724 MUX(0, "i2s0_clkout_s", i2s_clkout_p, 0,
725 4, 12, 1),
726 COMP(0, "i2s_src_s", cpll_gpll_p, 0,
727 4, 0, 7, 15, 1),
728
729 /* CRU_CLKSEL5_CON */
730 MUX(0, "spdif_src", cpll_gpll_p, 0,
731 5, 15, 1),
732 MUX(0, "spdif_mux", spdif_p, 0,
733 5, 8, 2),
734 CDIV(0, "spdif_pre_s", "spdif_src", 0,
735 5, 0, 7),
736
737 /* CRU_CLKSEL6_CON */
738 COMP(0, "sclk_isp_jpe_s", cpll_gpll_npll_p, 0,
739 6, 8, 6, 14, 2),
740 COMP(0, "sclk_isp_s", cpll_gpll_npll_p, 0,
741 6, 0, 6, 6, 2),
742
743 /* CRU_CLKSEL7_CON */
744 FRACT(0, "uart4_frac_s", "uart4_src", 0,
745 7),
746
747 /* CRU_CLKSEL8_CON */
748 FRACT(0, "i2s_frac_s", "i2s_src", 0,
749 8),
750
751 /* CRU_CLKSEL9_CON */
752 FRACT(0, "spdif_frac_s", "spdif_src", 0,
753 9),
754
755 /* CRU_CLKSEL10_CON */
756 CDIV(0, "pclk_peri_s", "aclk_peri_src", RK_CLK_COMPOSITE_DIV_EXP,
757 10, 12, 2),
758 CDIV(0, "hclk_peri_s", "aclk_peri_src", RK_CLK_COMPOSITE_DIV_EXP,
759 10, 8, 2),
760 COMP(0, "aclk_peri_src_s", cpll_gpll_p, 0,
761 10, 0, 5, 15, 1),
762
763 /* CRU_CLKSEL11_CON */
764 COMP(0, "sclk_sdmmc_s", mmc_p, 0,
765 11, 0, 6, 6, 2),
766
767 /* CRU_CLKSEL12_CON */
768 COMP(0, "sclk_emmc_s", mmc_p, 0,
769 12, 8, 6, 14, 2),
770 COMP(0, "sclk_sdio0_s", mmc_p, 0,
771 12, 0, 6, 6, 2),
772
773 /* CRU_CLKSEL13_CON */
774 MUX(0, "uart_src", cpll_gpll_p, 0,
775 13, 15, 1),
776 MUX(0, "usbphy480m_src_s", usbphy480m_p, 0,
777 13, 11, 2),
778 MUX(SCLK_UART0, "sclk_uart0", uart0_p, 0,
779 13, 8, 2),
780 COMP(0, "uart0_src_s", cpll_gpll_usb480m_npll_p, 0,
781 13, 0, 7, 13, 2),
782
783 /* CRU_CLKSEL14_CON */
784 MUX(SCLK_UART1, "sclk_uart1", uart1_p, 0,
785 14, 8, 2),
786 CDIV(0, "uart1_src_s", "uart_src", 0,
787 14, 0, 7),
788
789
790 /* CRU_CLKSEL15_CON */
791 MUX(SCLK_UART2, "sclk_uart2", uart2_p, 0,
792 15, 8, 2),
793 CDIV(0, "uart2_src_s", "uart_src", 0,
794 15, 0, 7),
795
796 /* CRU_CLKSEL16_CON */
797 MUX(SCLK_UART3, "sclk_uart3", uart3_p, 0,
798 16, 8, 2),
799 CDIV(0, "uart3_src_s", "uart_src", 0,
800 16, 0, 7),
801
802 /* CRU_CLKSEL17_CON */
803 FRACT(0, "uart0_frac_s", "uart0_src", 0,
804 17),
805
806 /* CRU_CLKSEL18_CON */
807 FRACT(0, "uart1_frac_s", "uart1_src", 0,
808 18),
809
810 /* CRU_CLKSEL19_CON */
811 FRACT(0, "uart2_frac_s", "uart2_src", 0,
812 19),
813
814 /* CRU_CLKSEL20_CON */
815 FRACT(0, "uart3_frac_s", "uart3_src", 0,
816 20),
817
818 /* CRU_CLKSEL21_CON */
819 COMP(0, "mac_pll_src_s", npll_cpll_gpll_p, 0,
820 21, 8, 5, 0, 2),
821 MUX(SCLK_MAC, "mac_clk", mac_p, 0,
822 21, 4, 1),
823
824 /* CRU_CLKSEL22_CON */
825 MUX(0, "sclk_hsadc_out", hsadcout_p, 0,
826 22, 4, 1),
827 COMP(0, "hsadc_src_s", cpll_gpll_p, 0,
828 22, 8, 8, 0, 1),
829 MUX(0, "wifi_src", wifi_p, 0,
830 22, 1, 1),
831 /* 7 - inverter "sclk_hsadc", "sclk_hsadc_out" */
832
833 /* CRU_CLKSEL23_CON */
834 FRACT(0, "wifi_frac_s", "wifi_src", 0,
835 23),
836
837 /* CRU_CLKSEL24_CON */
838 CDIV(0, "sclk_saradc_s", "xin24m", 0,
839 24, 8, 8),
840
841 /* CRU_CLKSEL25_CON */
842 COMP(0, "sclk_spi1_s", cpll_gpll_p, 0,
843 25, 8, 7, 15, 1),
844 COMP(0, "sclk_spi0_s", cpll_gpll_p, 0,
845 25, 0, 7, 7, 1),
846
847 /* CRU_CLKSEL26_CON */
848 COMP(SCLK_VIP_OUT, "sclk_vip_out", vip_out_p, 0,
849 26, 9, 5, 15, 1),
850 MUX(0, "vip_src_s", cpll_gpll_p, 0,
851 26, 8, 1),
852 CDIV(0, "crypto_s", "aclk_cpu_pre", 0,
853 26, 6, 2),
854 COMP(0, "ddrphy", ddrphy_p, RK_CLK_COMPOSITE_DIV_EXP,
855 26, 0, 2, 2, 1),
856
857 /* CRU_CLKSEL27_CON */
858 COMP(0, "dclk_vop0_s", cpll_gpll_npll_p, 0,
859 27, 8, 8, 0, 2),
860
861 MUX(0, "sclk_edp_24m_s", edp_24m_p, 0,
862 28, 15, 1),
863 CDIV(0, "hclk_vio", "aclk_vio0", 0,
864 28, 8, 5),
865 COMP(0, "sclk_edp_s", cpll_gpll_npll_p, 0,
866 28, 0, 6, 6, 2),
867
868 /* CRU_CLKSEL29_CON */
869 COMP(0, "dclk_vop1_s", cpll_gpll_npll_p, 0,
870 29, 8, 8, 6, 2),
871 /* 4 - inverter "pclk_vip" "pclk_vip_in" */
872 /* 3 - inverter "pclk_isp", "pclk_isp_in" */
873
874 /* CRU_CLKSEL30_CON */
875 COMP(0, "sclk_rga_s", cpll_gpll_usb480m_p, 0,
876 30, 8, 5, 14, 2),
877 COMP(0, "aclk_rga_pre_s", cpll_gpll_usb480m_p, 0,
878 30, 0, 5, 6, 2),
879
880 /* CRU_CLKSEL31_CON */
881 COMP(0, "aclk_vio1_s", cpll_gpll_usb480m_p, 0,
882 31, 8, 5, 14, 2),
883 COMP(0, "aclk_vio0_s", cpll_gpll_usb480m_p, 0,
884 31, 0, 5, 6, 2),
885
886 /* CRU_CLKSEL32_CON */
887 COMP(0, "aclk_vdpu_s", cpll_gpll_usb480m_p, 0,
888 32, 8, 5, 14, 2),
889 COMP(0, "aclk_vepu_s", cpll_gpll_usb480m_p, 0,
890 32, 0, 5, 6, 2),
891
892 /* CRU_CLKSEL33_CON */
893 CDIV(0, "pclk_pd_alive", "gpll", 0,
894 33, 8, 5),
895 CDIV(0, "pclk_pd_pmu_s", "gpll", 0,
896 33, 0, 5),
897
898 /* CRU_CLKSEL34_CON */
899 COMP(0, "sclk_sdio1_s", mmc_p, 0,
900 34, 8, 6, 14, 2),
901 COMP(0, "sclk_gpu_s", cpll_gpll_usb480m_npll_p, 0,
902 34, 0, 5, 6, 2),
903
904 /* CRU_CLKSEL35_CON */
905 COMP(0, "sclk_tspout_s", tspout_p, 0,
906 35, 8, 5, 14, 2),
907 COMP(0, "sclk_tsp_s", cpll_gpll_npll_p, 0,
908 35, 0, 5, 6, 2),
909
910 /* CRU_CLKSEL36_CON */
911 CDIV(0, "armcore3_s", "armclk", 0,
912 36, 12, 3),
913 CDIV(0, "armcore2_s", "armclk", 0,
914 36, 8, 3),
915 CDIV(0, "armcore1_s", "armclk", 0,
916 36, 4, 3),
917 CDIV(0, "armcore0_s", "armclk", 0,
918 36, 0, 3),
919
920 /* CRU_CLKSEL37_CON */
921 CDIV(0, "pclk_dbg_pre_s", "armclk", 0,
922 37, 9, 5),
923 CDIV(0, "atclk_s", "armclk", 0,
924 37, 4, 5),
925 CDIV(0, "l2ram_s", "armclk", 0,
926 37, 0, 3),
927
928 /* CRU_CLKSEL38_CON */
929 COMP(0, "sclk_nandc1_s", cpll_gpll_p, 0,
930 38, 8, 5, 15, 1),
931 COMP(0, "sclk_nandc0_s", cpll_gpll_p, 0,
932 38, 0, 5, 7, 1),
933
934 /* CRU_CLKSEL39_CON */
935 COMP(0, "aclk_hevc_s", cpll_gpll_npll_p, 0,
936 39, 8, 5, 14, 2),
937 COMP(0, "sclk_spi2_s", cpll_gpll_p, 0,
938 39, 0, 7, 7, 1),
939
940 /* CRU_CLKSEL40_CON */
941 CDIV(HCLK_HEVC, "hclk_hevc", "aclk_hevc", 0,
942 40, 12, 2),
943 MUX(0, "spdif_8ch_mux", spdif_8ch_p, 0,
944 40, 8, 2),
945 CDIV(0, "spdif_8ch_pre_s", "spdif_src", 0,
946 40, 0, 7),
947
948 /* CRU_CLKSEL41_CON */
949 FRACT(0, "spdif_8ch_frac_s", "spdif_8ch_pre", 0,
950 41),
951
952 /* CRU_CLKSEL42_CON */
953 COMP(0, "sclk_hevc_core_s", cpll_gpll_npll_p, 0,
954 42, 8, 5, 14, 2),
955 COMP(0, "sclk_hevc_cabac_s", cpll_gpll_npll_p, 0,
956 42, 0, 5, 6, 2),
957 /*
958 * not yet implemented MMC clocks
959 * id name src reg
960 * SCLK_SDMMC_DRV, "sdmmc_drv", "sclk_sdmmc", RK3288_SDMMC_CON0
961 * SCLK_SDMMC_SAMPLE, "sdmmc_sample", "sclk_sdmmc", RK3288_SDMMC_CON1,
962
963 * SCLK_SDIO0_DRV, "sdio0_drv", "sclk_sdio0", RK3288_SDIO0_CON0, 1),
964 * SCLK_SDIO0_SAMPLE, "sdio0_sample", "sclk_sdio0", RK3288_SDIO0_CON1, 0),
965
966 * SCLK_SDIO1_DRV, "sdio1_drv", "sclk_sdio1", RK3288_SDIO1_CON0, 1),
967 * SCLK_SDIO1_SAMPLE, "sdio1_sample", "sclk_sdio1", RK3288_SDIO1_CON1, 0),
968
969 * SCLK_EMMC_DRV, "emmc_drv", "sclk_emmc", RK3288_EMMC_CON0, 1),
970 * SCLK_EMMC_SAMPLE, "emmc_sample", "sclk_emmc", RK3288_EMMC_CON1, 0),
971 *
972 * and GFR based mux for "aclk_vcodec_pre"
973 */
974
975 };
976
977 static int
rk3288_cru_probe(device_t dev)978 rk3288_cru_probe(device_t dev)
979 {
980
981 if (!ofw_bus_status_okay(dev))
982 return (ENXIO);
983
984 if (ofw_bus_is_compatible(dev, "rockchip,rk3288-cru")) {
985 device_set_desc(dev, "Rockchip RK3288 Clock and Reset Unit");
986 return (BUS_PROBE_DEFAULT);
987 }
988
989 return (ENXIO);
990 }
991
992 static int
rk3288_cru_attach(device_t dev)993 rk3288_cru_attach(device_t dev)
994 {
995 struct rk_cru_softc *sc;
996
997 sc = device_get_softc(dev);
998 sc->dev = dev;
999
1000 sc->gates = rk3288_gates;
1001 sc->ngates = nitems(rk3288_gates);
1002
1003 sc->clks = rk3288_clks;
1004 sc->nclks = nitems(rk3288_clks);
1005
1006 sc->reset_num = CRU_SOFTRST_SIZE * 16;
1007 sc->reset_offset = CRU_SOFTRST_CON(0);
1008
1009 return (rk_cru_attach(dev));
1010 }
1011
1012 static device_method_t rk3288_cru_methods[] = {
1013 /* Device interface */
1014 DEVMETHOD(device_probe, rk3288_cru_probe),
1015 DEVMETHOD(device_attach, rk3288_cru_attach),
1016
1017 DEVMETHOD_END
1018 };
1019
1020 static devclass_t rk3288_cru_devclass;
1021
1022 DEFINE_CLASS_1(rk3288_cru, rk3288_cru_driver, rk3288_cru_methods,
1023 sizeof(struct rk_cru_softc), rk_cru_driver);
1024
1025 EARLY_DRIVER_MODULE(rk3288_cru, simplebus, rk3288_cru_driver,
1026 rk3288_cru_devclass, 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE + 1);
1027