| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | SIInstrInfo.h | 355 bool isSALU(uint16_t Opcode) const { in isSALU()
363 bool isVALU(uint16_t Opcode) const { in isVALU()
371 bool isVMEM(uint16_t Opcode) const { in isVMEM()
379 bool isSOP1(uint16_t Opcode) const { in isSOP1()
387 bool isSOP2(uint16_t Opcode) const { in isSOP2()
493 bool isDS(uint16_t Opcode) const { in isDS()
564 bool isEXP(uint16_t Opcode) const { in isEXP()
598 bool isWQM(uint16_t Opcode) const { in isWQM()
630 bool isDPP(uint16_t Opcode) const { in isDPP()
662 bool isMAI(uint16_t Opcode) const { in isMAI()
[all …]
|
| /llvm-project-15.0.7/lldb/source/Plugins/Instruction/PPC64/ |
| H A D | EmulateInstructionPPC64.h | 70 struct Opcode { struct
79 Opcode *GetOpcodeForInstruction(uint32_t opcode); argument
|
| /llvm-project-15.0.7/llvm/unittests/tools/llvm-exegesis/X86/ |
| H A D | SnippetGeneratorTest.cpp | 72 const unsigned Opcode = X86::ADC16i16; in TEST_F() local
98 const unsigned Opcode = X86::ADD16ri; in TEST_F() local
121 const unsigned Opcode = X86::VXORPSrr; in TEST_F() local
146 const unsigned Opcode = X86::VXORPSrr; in TEST_F() local
164 const unsigned Opcode = X86::CMP64rr; in TEST_F() local
185 const unsigned Opcode = X86::LAHF; in TEST_F() local
223 const unsigned Opcode = X86::CDQ; in TEST_F() local
249 const unsigned Opcode = X86::CMOV32rr; in TEST_F() local
317 const unsigned Opcode = X86::MOV32rm; in TEST_F() local
335 const unsigned Opcode = X86::MOV16ms; in TEST_F() local
[all …]
|
| /llvm-project-15.0.7/llvm/lib/Target/RISCV/ |
| H A D | RISCVMakeCompressible.cpp | 100 static unsigned log2LdstWidth(unsigned Opcode) { in log2LdstWidth()
119 static uint8_t compressedLDSTOffsetMask(unsigned Opcode) { in compressedLDSTOffsetMask()
125 static bool compressibleSPOffset(int64_t Offset, unsigned Opcode) { in compressibleSPOffset()
133 static int64_t getBaseAdjustForCompression(int64_t Offset, unsigned Opcode) { in getBaseAdjustForCompression()
148 const unsigned Opcode = MI.getOpcode(); in isCompressibleLoad() local
157 const unsigned Opcode = MI.getOpcode(); in isCompressibleStore() local
176 const unsigned Opcode = MI.getOpcode(); in getRegImmPairPreventingCompression() local
289 unsigned Opcode = MI.getOpcode(); in updateOperands() local
367 unsigned Opcode = RISCV::FPR32RegClass.contains(RegImm.Reg) in runOnMachineFunction() local
|
| /llvm-project-15.0.7/llvm/lib/Target/Lanai/ |
| H A D | LanaiInstrInfo.h | 146 static inline bool isSPLSOpcode(unsigned Opcode) { in isSPLSOpcode()
160 static inline bool isRMOpcode(unsigned Opcode) { in isRMOpcode()
170 static inline bool isRRMOpcode(unsigned Opcode) { in isRRMOpcode()
|
| H A D | LanaiRegisterInfo.cpp | 69 static bool isALUArithLoOpcode(unsigned Opcode) { in isALUArithLoOpcode()
85 static unsigned getOppositeALULoOpcode(unsigned Opcode) { in getOppositeALULoOpcode()
108 static unsigned getRRMOpcodeVariant(unsigned Opcode) { in getRRMOpcodeVariant()
|
| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/ |
| H A D | TargetOpcodes.h | 30 inline bool isPreISelGenericOpcode(unsigned Opcode) { in isPreISelGenericOpcode()
36 inline bool isTargetSpecificOpcode(unsigned Opcode) { in isTargetSpecificOpcode()
42 inline bool isPreISelGenericOptimizationHint(unsigned Opcode) { in isPreISelGenericOptimizationHint()
|
| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| H A D | PPCPredicates.cpp | 18 PPC::Predicate PPC::InvertPredicate(PPC::Predicate Opcode) { in InvertPredicate()
52 PPC::Predicate PPC::getSwappedPredicate(PPC::Predicate Opcode) { in getSwappedPredicate()
|
| /llvm-project-15.0.7/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMUnwindOpAsm.h | 72 void EmitInt8(unsigned Opcode) { in EmitInt8()
77 void EmitInt16(unsigned Opcode) { in EmitInt16()
83 void emitBytes(const uint8_t *Opcode, size_t Size) { in emitBytes()
|
| /llvm-project-15.0.7/llvm/unittests/tools/llvm-exegesis/PowerPC/ |
| H A D | SnippetGeneratorTest.cpp | 37 std::vector<CodeTemplate> checkAndGetCodeTemplates(unsigned Opcode) { in checkAndGetCodeTemplates()
63 const unsigned Opcode = PPC::ADD8; in TEST_F() local
93 const unsigned Opcode = PPC::RLDIMI; in TEST_F() local
116 const unsigned Opcode = PPC::LDX; in TEST_F() local
|
| /llvm-project-15.0.7/llvm/lib/Target/SystemZ/ |
| H A D | SystemZShortenInst.cpp | 110 bool SystemZShortenInst::shortenOn0(MachineInstr &MI, unsigned Opcode) { in shortenOn0()
120 bool SystemZShortenInst::shortenOn01(MachineInstr &MI, unsigned Opcode) { in shortenOn01()
132 bool SystemZShortenInst::shortenOn001(MachineInstr &MI, unsigned Opcode) { in shortenOn001()
145 bool SystemZShortenInst::shortenOn001AddCC(MachineInstr &MI, unsigned Opcode) { in shortenOn001AddCC()
158 bool SystemZShortenInst::shortenFPConv(MachineInstr &MI, unsigned Opcode) { in shortenFPConv()
180 bool SystemZShortenInst::shortenFusedFPOp(MachineInstr &MI, unsigned Opcode) { in shortenFusedFPOp()
|
| /llvm-project-15.0.7/llvm/tools/llvm-readobj/ |
| H A D | ARMEHABIPrinter.h | 99 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_00xxxxxx() local
105 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_01xxxxxx() local
124 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_10011101() local
129 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_10011111() local
134 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_1001nnnn() local
139 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_10100nnn() local
146 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_10101nnn() local
153 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_10110000() local
169 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_10110010_uleb128() local
196 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_101101nn() local
[all …]
|
| /llvm-project-15.0.7/lldb/include/lldb/Core/ |
| H A D | Opcode.h | 43 Opcode(uint8_t inst, lldb::ByteOrder order) in Opcode() function
48 Opcode(uint16_t inst, lldb::ByteOrder order) in Opcode() function
53 Opcode(uint32_t inst, lldb::ByteOrder order) in Opcode() function
58 Opcode(uint64_t inst, lldb::ByteOrder order) in Opcode() function
63 Opcode(uint8_t *bytes, size_t length) in Opcode() function
|
| /llvm-project-15.0.7/llvm/unittests/tools/llvm-exegesis/Mips/ |
| H A D | SnippetGeneratorTest.cpp | 37 std::vector<CodeTemplate> checkAndGetCodeTemplates(unsigned Opcode) { in checkAndGetCodeTemplates()
63 const unsigned Opcode = Mips::ADD; in TEST_F() local
108 const unsigned Opcode = Mips::LB; in TEST_F() local
|
| /llvm-project-15.0.7/llvm/lib/Target/Sparc/ |
| H A D | LeonPasses.cpp | 48 unsigned Opcode = MI.getOpcode(); in runOnMachineFunction() local
81 unsigned Opcode = MI.getOpcode(); in runOnMachineFunction() local
132 unsigned Opcode = MI.getOpcode(); in runOnMachineFunction() local
|
| /llvm-project-15.0.7/llvm/include/llvm/MC/ |
| H A D | MCInstrInfo.h | 63 const MCInstrDesc &get(unsigned Opcode) const { in get()
69 StringRef getName(unsigned Opcode) const { in getName()
|
| /llvm-project-15.0.7/llvm/lib/Target/BPF/ |
| H A D | BPFMISimplifyPatchable.cpp | 96 bool BPFMISimplifyPatchable::isLoadInst(unsigned Opcode) { in isLoadInst()
118 unsigned Opcode = DefInst->getOpcode(); in checkADDrr() local
156 unsigned Opcode) { in checkShift()
186 unsigned Opcode = I->getParent()->getOpcode(); in processCandidate() local
242 unsigned Opcode = Inst->getOpcode(); in processInst() local
|
| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | LegacyLegalizerInfo.h | 84 unsigned Opcode; member
179 void setLegalizeScalarToDifferentSizeStrategy(const unsigned Opcode, in setLegalizeScalarToDifferentSizeStrategy()
190 void setLegalizeVectorElementToDifferentSizeStrategy(const unsigned Opcode, in setLegalizeVectorElementToDifferentSizeStrategy()
320 void setScalarAction(const unsigned Opcode, const unsigned TypeIndex, in setScalarAction()
326 void setPointerAction(const unsigned Opcode, const unsigned TypeIndex, in setPointerAction()
343 void setScalarInVectorAction(const unsigned Opcode, const unsigned TypeIndex, in setScalarInVectorAction()
354 void setVectorNumElementAction(const unsigned Opcode, in setVectorNumElementAction()
|
| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonTargetTransformInfo.cpp | 160 InstructionCost HexagonTTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src, in getMemoryOpCost()
217 HexagonTTIImpl::getMaskedMemoryOpCost(unsigned Opcode, Type *Src, in getMaskedMemoryOpCost()
232 unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, in getGatherScatterOpCost()
239 unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices, in getInterleavedMemoryOpCost()
251 InstructionCost HexagonTTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, in getCmpSelInstrCost()
265 unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, in getArithmeticInstrCost()
285 InstructionCost HexagonTTIImpl::getCastInstrCost(unsigned Opcode, Type *DstTy, in getCastInstrCost()
308 InstructionCost HexagonTTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, in getVectorInstrCost()
|
| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMSelectionDAGInfo.h | 23 static inline ShiftOpc getShiftOpcForNode(unsigned Opcode) { in getShiftOpcForNode()
|
| H A D | ARMBaseInstrInfo.h | 499 bool isFpMLxInstruction(unsigned Opcode) const { in isFpMLxInstruction()
513 bool canCauseFpMLxStall(unsigned Opcode) const { in canCauseFpMLxStall()
586 unsigned VCMPOpcodeToVPT(unsigned Opcode) { in VCMPOpcodeToVPT()
895 inline bool isLegalAddressImm(unsigned Opcode, int Imm, in isLegalAddressImm()
|
| /llvm-project-15.0.7/clang/lib/AST/Interp/ |
| H A D | Opcode.h | 21 enum Opcode : uint32_t { enum
|
| /llvm-project-15.0.7/llvm/unittests/Target/ARM/ |
| H A D | MachineInstrTest.cpp | 16 auto DoubleWidthResult = [](unsigned Opcode) { in TEST()
113 auto HorizontalReduction = [](unsigned Opcode) { in TEST()
269 auto RetainsPreviousHalfElement = [](unsigned Opcode) { in TEST()
379 auto IsValidTPOpcode = [](unsigned Opcode) { in TEST()
1222 auto MVEVecSize = [](unsigned Opcode) { in TEST()
|
| /llvm-project-15.0.7/llvm/lib/Target/XCore/ |
| H A D | XCoreFrameLowering.cpp | 106 int Opcode = isImmU6(OpImm) ? XCore::EXTSP_u6 : XCore::EXTSP_lu6; in IfNeededExtSP() local
128 int Opcode = isImmU6(OpImm) ? XCore::LDAWSP_ru6 : XCore::LDAWSP_lru6; in IfNeededLDAWSP() local
201 int Opcode = isImmU6(Offset) ? XCore::LDWSP_ru6 : XCore::LDWSP_lru6; in RestoreSpillList() local
262 int Opcode = isImmU6(Adjusted) ? XCore::ENTSP_u6 : XCore::ENTSP_lu6; in emitPrologue() local
287 int Opcode = isImmU6(Offset) ? XCore::STWSP_ru6 : XCore::STWSP_lru6; in emitPrologue() local
400 int Opcode = isImmU6(RemainingAdj) ? XCore::RETSP_u6 : XCore::RETSP_lu6; in emitEpilogue() local
407 int Opcode = isImmU6(RemainingAdj) ? XCore::LDAWSP_ru6 : in emitEpilogue() local
510 int Opcode = isU6 ? XCore::EXTSP_u6 : XCore::EXTSP_lu6; in eliminateCallFramePseudoInstr() local
514 int Opcode = isU6 ? XCore::LDAWSP_ru6 : XCore::LDAWSP_lru6; in eliminateCallFramePseudoInstr() local
|
| /llvm-project-15.0.7/llvm/lib/MC/ |
| H A D | MCInstrInfo.cpp | 17 unsigned Opcode = MI.getOpcode(); in getDeprecatedInfo() local
|