| /wasmtime-44.0.1/cranelift/codegen/src/isa/s390x/inst/ |
| H A D | emit_tests.rs | 537 index: zero_reg(), in test_s390x_binemit()
552 index: zero_reg(), in test_s390x_binemit()
567 index: zero_reg(), in test_s390x_binemit()
582 index: zero_reg(), in test_s390x_binemit()
597 index: zero_reg(), in test_s390x_binemit()
612 index: zero_reg(), in test_s390x_binemit()
627 index: zero_reg(), in test_s390x_binemit()
642 index: zero_reg(), in test_s390x_binemit()
657 index: zero_reg(), in test_s390x_binemit()
672 index: zero_reg(), in test_s390x_binemit()
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| H A D | args.rs | 82 index: zero_reg(), in reg()
191 if base != zero_reg() { in pretty_print()
192 if index != zero_reg() { in pretty_print()
203 if index != zero_reg() { in pretty_print()
213 if base != zero_reg() { in pretty_print()
214 if index != zero_reg() { in pretty_print()
225 if index != zero_reg() { in pretty_print()
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| H A D | regs.rs | 76 pub fn zero_reg() -> Reg { in zero_reg() function
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| H A D | emit.rs | 154 index: zero_reg(),
161 index: zero_reg(),
190 index != zero_reg()
335 assert!(index == zero_reg()); in mem_rs_emit()
341 assert!(index == zero_reg()); in mem_rs_emit()
386 assert!(index == zero_reg()); in mem_imm8_emit()
392 assert!(index == zero_reg()); in mem_imm8_emit()
433 assert!(index == zero_reg()); in mem_imm16_emit()
3297 && lane_reg == zero_reg() in emit_with_alloc_consumer()
3399 shift_reg: zero_reg(), in emit_with_alloc_consumer()
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| /wasmtime-44.0.1/cranelift/isle/veri/veri_engine/examples/broken/ |
| H A D | broken_32_general_rotl_to_rotr.isle | 15 (spec (zero_reg)
17 (decl zero_reg () Reg)
18 (extern constructor zero_reg zero_reg)
33 (neg_shift Reg (sub $I32 amt (zero_reg))))
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| H A D | broken_imul.isle | 37 (spec (zero_reg)
39 (decl zero_reg () Reg)
40 (extern constructor zero_reg zero_reg)
59 (madd ty y y (zero_reg)))
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| H A D | broken_mask_small_rotr.isle | 8 (spec (zero_reg)
10 (decl zero_reg () Reg)
11 (extern constructor zero_reg zero_reg)
134 (neg_amt Reg (sub $I32 (zero_reg) tmp_sub))
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| H A D | broken_rule_or_small_rotr.isle | 8 (spec (zero_reg)
10 (decl zero_reg () Reg)
11 (extern constructor zero_reg zero_reg)
146 (neg_amt Reg (sub $I32 (zero_reg) tmp_sub))
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| H A D | broken_fits_in_16_rotl_to_rotr.isle | 12 (spec (zero_reg)(provide (= (zero_ext 64 #x0000000000000000) result)))
13 (decl zero_reg () Reg)
14 (extern constructor zero_reg zero_reg)
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| H A D | broken_fits_in_16_with_imm_rotl_to_rotr.isle | 13 (spec (zero_reg)
15 (decl zero_reg () Reg)
16 (extern constructor zero_reg zero_reg)
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| /wasmtime-44.0.1/cranelift/isle/veri/veri_engine/examples/broken/imul/ |
| H A D | broken_imul.isle | 37 (spec (zero_reg)
39 (decl zero_reg () Reg)
40 (extern constructor zero_reg zero_reg)
59 (madd ty y y (zero_reg)))
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| /wasmtime-44.0.1/cranelift/codegen/src/isa/riscv64/inst/ |
| H A D | emit_tests.rs | 277 rs2: zero_reg(), in test_riscv64_binemit()
299 rs2: zero_reg(), in test_riscv64_binemit()
309 rs2: zero_reg(), in test_riscv64_binemit()
320 rs2: zero_reg(), in test_riscv64_binemit()
331 rs2: zero_reg(), in test_riscv64_binemit()
341 rs2: zero_reg(), in test_riscv64_binemit()
352 rs2: zero_reg(), in test_riscv64_binemit()
363 rs2: zero_reg(), in test_riscv64_binemit()
374 rs2: zero_reg(), in test_riscv64_binemit()
385 rs2: zero_reg(), in test_riscv64_binemit()
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| H A D | emit.rs | 323 && rs1 != zero_reg() in try_emit_compressed()
324 && rs2 != zero_reg() => in try_emit_compressed()
342 && rs != zero_reg() in try_emit_compressed()
404 if rd.to_reg() == zero_reg() && base != zero_reg() && offset.as_i16() == 0 => in try_emit_compressed()
423 zero_reg(), in try_emit_compressed()
482 } if rd.to_reg() != zero_reg() && rs == zero_reg() => { in try_emit_compressed()
845 && rs2 == zero_reg() => in try_emit_compressed()
872 rs: zero_reg(), in emit_uncompressed()
1740 src: zero_reg(), in emit_uncompressed()
1823 src: zero_reg(), in emit_uncompressed()
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| H A D | regs.rs | 63 pub fn zero_reg() -> Reg { in zero_reg() function
70 Writable::from_reg(zero_reg()) in writable_zero_reg()
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| H A D | mod.rs | 133 rs: zero_reg(), in load_imm12()
150 zero_reg() in load_const_imm()
1162 AluOPRRR::Adduw if rs2 == zero_reg() => { in print_with_state()
1240 (AluOPRRI::Addi, rs, _) if rs == zero_reg() => { in print_with_state()
1265 (CsrRegOP::CsrRW, CSR::Frm, rd) if rd.to_reg() == zero_reg() => { in print_with_state()
1277 (CsrImmOP::CsrRWI, CSR::Frm, rd) if rd.to_reg() != zero_reg() => { in print_with_state()
1580 (VecAluOpRRR::VrsubVX, _, vs1) if vs1 == zero_reg() => { in print_with_state()
1871 insn2 | enc_jalr(writable_zero_reg(), zero_reg(), imm12), in patch_raw_offset()
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| /wasmtime-44.0.1/cranelift/codegen/src/isa/aarch64/inst/ |
| H A D | regs.rs | 56 pub fn zero_reg() -> Reg { in zero_reg() function
63 Writable::from_reg(zero_reg()) in writable_zero_reg()
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| H A D | emit.rs | 1368 sink.put4(enc_arith_rrr(0b10101010_000, 0b000_000, rd, zero_reg(), rm)); in emit()
1376 sink.put4(enc_arith_rrr(0b00101010_000, 0b000_000, rd, zero_reg(), rm)); in emit()
1426 sink.put4(enc_csel(rd, zero_reg(), zero_reg(), cond.invert(), 0, 1)); in emit()
1429 sink.put4(enc_csel(rd, zero_reg(), zero_reg(), cond.invert(), 1, 0)); in emit()
1483 let xzr = zero_reg(); in emit()
3189 rn: zero_reg(), in emit()
3605 rd: regs::zero_reg(), in emit()
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| /wasmtime-44.0.1/cranelift/codegen/src/isa/riscv64/lower/ |
| H A D | isle.rs | 407 fn zero_reg(&mut self) -> XReg { in zero_reg() method
408 XReg::new(zero_reg()).unwrap() in zero_reg()
411 if reg != self.zero_reg() { in is_non_zero_reg()
418 if reg == self.zero_reg() { in is_zero_reg()
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| /wasmtime-44.0.1/cranelift/codegen/src/isa/riscv64/ |
| H A D | inst.isle | 1197 (rv_sltu (zero_reg) rs1))
1610 (rv_adduw rs1 (zero_reg)))
1909 (rv_addi (zero_reg) imm12))
1957 (rv_addi (zero_reg) (imm12_const x)))
2251 (rv_packw val (zero_reg)))
2256 (rv_pack val (zero_reg)))
2708 (rule 3 (gen_select_xreg (int_compare_decompose (IntCC.Equal) c (zero_reg)) x (zero_reg))
2712 (rule 3 (gen_select_xreg (int_compare_decompose (IntCC.NotEqual) c (zero_reg)) x (zero_reg))
2983 (zero_reg))
3197 (decl zero_reg () XReg)
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| H A D | lower.isle | 521 (dst_lo XReg (madd x_lo y_lo (zero_reg))))
658 no_int_overflow (zero_reg)
1344 (value_regs (zero_reg) low)
1399 (value_regs high (zero_reg))
1746 (zero_reg))
1931 (gen_select_xreg (is_nonzero_cmp c) (zero_reg) y))
1934 (gen_select_xreg (is_nonzero_cmp c) x (zero_reg)))
2522 (min FReg (rv_fmvdx (zero_reg)))
3088 (let ((zero VReg (rv_vmv_vx (zero_reg) ty))
3095 (let ((zero VReg (rv_vmv_vx (zero_reg) ty))
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| /wasmtime-44.0.1/cranelift/codegen/src/isa/aarch64/ |
| H A D | lower.isle | 780 (sub ty (zero_reg) x))
794 (madd ty x y (zero_reg)))
833 (madd $I64 x y (zero_reg))
841 (madd $I64 x y (zero_reg))
1008 (mul Reg (madd $I64 x64 y64 (zero_reg)))
1339 (orr_not ty (zero_reg) x))
1365 (orr_not_shift ty (zero_reg) x amt))
1541 (csel (Cond.Ne) (zero_reg) lo_lshift)
2264 (cmp (OperandSize.Size64) rt (zero_reg))
3123 (out Reg (umaddl a b (zero_reg)))
[all …]
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| /wasmtime-44.0.1/cranelift/codegen/src/isa/s390x/ |
| H A D | lower.isle | 65 (x_hi Reg (vec_extract_lane $I64X2 x_reg 0 (zero_reg)))
442 (let ((x_hi Reg (vec_extract_lane $I64X2 x 0 (zero_reg)))
443 (x_lo Reg (vec_extract_lane $I64X2 x 1 (zero_reg)))
444 (y_hi Reg (vec_extract_lane $I64X2 y 0 (zero_reg)))
982 (vec_extract_lane $I64X2 x 1 (zero_reg)))
2112 (vec_insert_lane_undef $F64X2 x 0 (zero_reg)))
2116 (vec_extract_lane $F64X2 x 0 (zero_reg)))
2120 (vec_insert_lane_undef $F32X4 x 0 (zero_reg)))
2124 (vec_extract_lane $F32X4 x 0 (zero_reg)))
2128 (vec_insert_lane_undef $F16X8 x 0 (zero_reg)))
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| H A D | inst.isle | 1638 (decl zero_reg () Reg)
1639 (extern constructor zero_reg zero_reg)
1809 (vec_extract_lane $I64X2 amt 1 (zero_reg)))
1815 (vec_insert_lane_undef $I8X16 amt 0 (zero_reg)) 0))
4441 (shift_rr ty (shiftop_rot ty) x shift_imm (zero_reg)))
4463 (vec_shift_rr ty (vec_shiftop_rot ty) x shift_imm (zero_reg)))
4480 (shift_rr ty (shiftop_lshl ty) x shift_imm (zero_reg)))
4494 (vec_shift_rr ty (vec_shiftop_lshl ty) x shift_imm (zero_reg)))
4515 (shift_rr ty (shiftop_lshr ty) x shift_imm (zero_reg)))
4529 (vec_shift_rr ty (vec_shiftop_lshr ty) x shift_imm (zero_reg)))
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| /wasmtime-44.0.1/cranelift/codegen/src/isa/aarch64/lower/ |
| H A D | isle.rs | 13 stack_reg, writable_link_reg, writable_zero_reg, zero_reg,
410 fn zero_reg(&mut self) -> Reg { in zero_reg() method
411 zero_reg() in zero_reg()
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| /wasmtime-44.0.1/cranelift/codegen/src/isa/s390x/lower/ |
| H A D | isle.rs | 13 writable_gpr, zero_reg,
293 fn zero_reg(&mut self) -> Reg { in zero_reg() method
294 zero_reg() in zero_reg()
|