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/wasmtime-44.0.1/cranelift/bforest/src/
H A Dpool.rs138 let upper = keys.get(i).cloned().or(rkey); in verify_tree() localVariable
141 if let (Some(a), Some(b)) = (lower, upper) { in verify_tree()
154 todo.push((lower, tree[i], upper)); in verify_tree()
157 lower = upper; in verify_tree()
179 let upper = keys.get(i).cloned().or(rkey); in verify_tree() localVariable
182 if let (Some(a), Some(b)) = (lower, upper) { in verify_tree()
200 lower = upper; in verify_tree()
/wasmtime-44.0.1/cranelift/filetests/filetests/runtests/
H A Dissue-10906.clif2 ;; sure to zero out the upper bits before inserting the `i16` into the lowest
H A Dbr_table.clif112 ; The riscv64 backend was failing to clear the upper half of the
H A Dinteger-minmax.clif146 ; make sure that upper/uninitialized parts of operand registers do not leak
/wasmtime-44.0.1/crates/wasi/src/p3/filesystem/
H A Dmod.rs227 crate::filesystem::MetadataHashValue { lower, upper }: crate::filesystem::MetadataHashValue,
229 Self { lower, upper }
/wasmtime-44.0.1/crates/wasi/src/
H A Dfilesystem.rs324 pub upper: u64, field
348 let upper = lower ^ 4614256656552045848u64; in from() localVariable
349 Self { lower, upper } in from()
639 MetadataHashValue::from(&meta_a).upper, in is_same_object()
640 MetadataHashValue::from(&meta_b).upper, in is_same_object()
/wasmtime-44.0.1/cranelift/codegen/src/isa/x64/
H A Dlower.isle2087 ;; flipping the upper bit works.
2113 ;; `pcmpgt` for why flipping the upper bit works.
2229 ;; on the CC provided for the upper/lower halves.
2281 (x64_cmpq_mi_sxb upper 64)
2282 (cmove $I64 (CC.NZ) upper lower))))
2315 (upper Gpr (x64_add $I64
2321 (cmove $I64 (CC.Z) upper lower))))
2356 (x64_cmpq_mi_sxb upper 63)
3759 ;; half and one for the upper half.
4807 ;; the upper lanes.
[all …]
H A Dinst.isle1229 ;; opcodes on 32-bits will zero-extend the upper 32-bits, so we can
1269 ;; be a 32-bit operation, will automatically zero the upper 32-bits of the
1922 ;; Note that if `Type` is less than 64-bits then the upper bits of the `imm`
2453 ;; register where the upper bits are from the first operand and the low
2975 ;; the upper bits of the first register and only performs the square root
3163 ;; the upper bit of `xlo` and `ylo` is flipped to change the sign when compared
3168 ;; * if xlo had an upper bit of 0 and ylo had an upper bit of 1, then xlo > ylo
3171 ;; * if xlo had an upper bit of 1 and ylo had an upper bit of 0, then xlo > ylo
3175 ;; Given all that the sequence here is to flip the upper bits of xlo and ylo,
3177 ;; are not equal then the gt result for the upper bits is used. If the upper
[all …]
/wasmtime-44.0.1/pulley/src/
H A Dregs.rs263 fn from(upper: UpperRegSet<R>) -> ScalarBitSet<u16> { in from()
264 upper.bitset in from()
/wasmtime-44.0.1/crates/wasi/src/p2/host/filesystem/
H A Dsync.rs514 upper: other.upper, in from()
/wasmtime-44.0.1/crates/wasi/src/p2/host/
H A Dfilesystem.rs578 crate::filesystem::MetadataHashValue { lower, upper }: crate::filesystem::MetadataHashValue,
580 Self { lower, upper }
/wasmtime-44.0.1/cranelift/entity/src/
H A Dlist.rs471 let (len, upper) = iterator.size_hint(); in extend()
473 if upper == Some(len) { in extend()
/wasmtime-44.0.1/crates/wasi-http/src/p3/
H A Dbody.rs669 } else if let Some(max) = hint.upper() { in size_hint()
/wasmtime-44.0.1/cranelift/codegen/src/isa/aarch64/
H A Dlower.isle824 ;; Special cases where the upper bits are sign-or-zero extended of the lower bits
1242 ;; Atomic loads will also automatically zero their upper bits so the `uextend`
1249 ;; Conversion to 128-bit needs a zero-extension of the lower bits and the upper
1255 ;; i128 only requires generating a 0 constant for the upper bits.
1289 ;; 64-bit to 128-bit only needs to sign-extend the input to the upper bits.
1296 ;; i128 only requires generating a 0 constant for the upper bits.
1769 ;; Note that when negating the shift amount here the upper bits are ignored
2840 ;; extractlane with lane 0 can pass through the value unchanged; upper
2892 ;; Produce a version of `anded` with upper 8 lanes and
2936 ;; LSB, and add with a left-shift of upper lane's MSB back
/wasmtime-44.0.1/cranelift/isle/veri/
H A DREADME.md174 …and `e : (bv N)` converts the bitvector `e` to the width `w`, leaving the upper bits unspecified i…
/wasmtime-44.0.1/pulley/
H A DCONTRIBUTING.md74 by the disassembler and visitor trait, the upper-camel-case name of the
/wasmtime-44.0.1/cranelift/codegen/src/
H A Dprelude.isle114 ;; Each of these extractors tests whether the upper half of the input equals the
/wasmtime-44.0.1/crates/debugger/wit/deps/
H A Dfilesystem.wit291 upper: u64,
/wasmtime-44.0.1/crates/wasi/src/p2/wit/deps/
H A Dfilesystem.wit291 upper: u64,
/wasmtime-44.0.1/crates/wasi-http/wit/deps/
H A Dfilesystem.wit291 upper: u64,
/wasmtime-44.0.1/crates/wasi-http/src/p3/wit/deps/
H A Dfilesystem.wit304 upper: u64,
/wasmtime-44.0.1/crates/wasi/src/p3/wit/deps/
H A Dfilesystem.wit304 upper: u64,
/wasmtime-44.0.1/cranelift/codegen/src/isa/pulley_shared/
H A Dlower.isle828 ;; Compare both the bottom and upper halves of the 128-bit values. If
829 ;; the top half is equal use the bottom comparison, otherwise use the upper
/wasmtime-44.0.1/cranelift/codegen/src/isa/riscv64/
H A Dlower.isle1786 ;; `vfncvt...` leaves the upper bits of the register undefined so
2394 ;; Compare both the bottom and upper halves of the 128-bit values. If
2395 ;; the top half is equal use the bottom comparison, otherwise use the upper
H A Dinst.isle2919 ;; Note that non-64-bit types need to be extended since the upper bits from
3154 ;; register is defined. For i128 we test both the upper and lower half.

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