Home
last modified time | relevance | path

Searched refs:src1 (Results 1 – 25 of 29) sorted by relevance

12

/wasmtime-44.0.1/cranelift/codegen/src/isa/pulley_shared/inst/
H A Dargs.rs398 Cond::IfXeq32 { src1, src2 } => Cond::IfXneq32 { src1, src2 }, in invert()
399 Cond::IfXneq32 { src1, src2 } => Cond::IfXeq32 { src1, src2 }, in invert()
400 Cond::IfXeq64 { src1, src2 } => Cond::IfXneq64 { src1, src2 }, in invert()
401 Cond::IfXneq64 { src1, src2 } => Cond::IfXeq64 { src1, src2 }, in invert()
438 Cond::IfXeq32I32 { src1, src2 } => Cond::IfXneq32I32 { src1, src2 }, in invert()
439 Cond::IfXneq32I32 { src1, src2 } => Cond::IfXeq32I32 { src1, src2 }, in invert()
440 Cond::IfXslt32I32 { src1, src2 } => Cond::IfXsgteq32I32 { src1, src2 }, in invert()
441 Cond::IfXslteq32I32 { src1, src2 } => Cond::IfXsgt32I32 { src1, src2 }, in invert()
442 Cond::IfXult32I32 { src1, src2 } => Cond::IfXugteq32I32 { src1, src2 }, in invert()
449 Cond::IfXeq64I32 { src1, src2 } => Cond::IfXneq64I32 { src1, src2 }, in invert()
[all …]
/wasmtime-44.0.1/cranelift/codegen/src/isa/x64/
H A Dinst.isle1783 (rule (x64_imul $I16 src1 src2) (x64_imulw_rm src1 src2))
1784 (rule (x64_imul $I32 src1 src2) (x64_imull_rm src1 src2))
1785 (rule (x64_imul $I64 src1 src2) (x64_imulq_rm src1 src2))
1908 (rule (x64_andn $I8 src1 src2) (x64_andnl_rvm src1 src2))
2308 (rule (x64_pand src1 src2) (x64_pand_a_or_avx src1 src2))
2318 (rule (x64_por src1 src2) (x64_por_a_or_avx src1 src2))
2660 (rule (x64_vpmullq src1 src2) (x64_vpmullq_c src1 src2))
2703 (rule (x64_vpsraq src1 src2) (x64_vpsraq_g src1 src2))
2850 (rule (x64_bt $I16 src1 src2) (x64_btw_mr src1 src2))
2851 (rule (x64_bt $I32 src1 src2) (x64_btl_mr src1 src2))
[all …]
/wasmtime-44.0.1/winch/codegen/src/isa/x64/
H A Dasm.rs1756 src1: Reg, in xmm_vpaddus_rrm()
1797 src1: Reg, in xmm_vpadd_rmr()
1872 src1: Reg, in xmm_vpinsr_rrm()
1895 src1: Reg, in xmm_vpinsr_rrr()
1982 pub fn xmm_vptest(&mut self, src1: Reg, src2: Reg) { in xmm_vptest()
1983 let inst = asm::inst::vptest_rm::new(src1, src2).into(); in xmm_vptest()
2050 src1: Reg, in xmm_vaddp_rrm()
2264 src1: Reg, in xmm_vunpcklp_rrm()
2448 src1: Reg, in xmm_vandp_rrm()
2576 src1: Reg, in xmm_vminp_rrm()
[all …]
H A Dmasm.rs928 src1: Reg, in float_cmp_with_set()
939 let (src1, src2, set_kind) = match kind { in float_cmp_with_set()
953 self.asm.ucomis(src1, src2, size); in float_cmp_with_set()
1977 self.asm.xmm_vpand_rrr(src1, src2, dst); in v128_and()
1989 self.asm.xmm_vpor_rrr(dst, src1, src2); in v128_or()
1995 self.asm.xmm_vpxor_rrr(src1, src2, dst); in v128_xor()
2090 src1: Reg, in v128_narrow()
2838 src1: Reg, in v128_min()
2909 src1: Reg, in v128_max()
2997 self.v128_extend(src1.reg, writable!(src1.reg), ext_kind)?; in v128_extmul()
[all …]
/wasmtime-44.0.1/pulley/src/
H A Dinterp.rs1713 let a = self.state[src1].get_u32(); in xadd32_u32()
1730 let a = self.state[src1].get_u64(); in xadd64_u32()
1736 let a = self.state[src1].get_u32(); in xmadd32()
1744 let a = self.state[src1].get_u64(); in xmadd64()
1763 let a = self.state[src1].get_u32(); in xsub32_u32()
1780 let a = self.state[src1].get_u64(); in xsub64_u32()
1797 let a = self.state[src1].get_i32(); in xmul32_s32()
1814 let a = self.state[src1].get_i64(); in xmul64_s32()
2277 let a = self.state[src1].get_i32(); in xband32_s32()
2294 let a = self.state[src1].get_i64(); in xband64_s32()
[all …]
H A Dregs.rs175 pub src1: S1, field
182 pub fn new(dst: impl Into<D>, src1: impl Into<S1>, src2: impl Into<S2>) -> Self { in new()
185 src1: src1.into(), in new()
195 let src1 = self.src1.to_u8(); in to_bits() localVariable
197 (dst as u16) | ((src1 as u16) << 5) | ((src2 as u16) << 10) in to_bits()
204 src1: S1::new(((bits >> 5) & 0b11111) as u8).unwrap(), in from_bits()
214 let src1 = self.src1.to_u8(); in to_bits() localVariable
216 (dst as u16) | ((src1 as u16) << 5) | ((src2 as u16) << 10) in to_bits()
223 src1: S1::new(((bits >> 5) & 0b11111) as u8).unwrap(), in from_bits()
498 for src1 in XReg::RANGE { in binary_operands()
[all …]
H A Dlib.rs270 xadd32_u8 = Xadd32U8 { dst: XReg, src1: XReg, src2: u8 };
277 xadd64_u8 = Xadd64U8 { dst: XReg, src1: XReg, src2: u8 };
291 xsub32_u8 = Xsub32U8 { dst: XReg, src1: XReg, src2: u8 };
298 xsub64_u8 = Xsub64U8 { dst: XReg, src1: XReg, src2: u8 };
305 xmul32_s8 = Xmul32S8 { dst: XReg, src1: XReg, src2: i8 };
777 feq32 = Feq32 { dst: XReg, src1: FReg, src2: FReg };
779 fneq32 = Fneq32 { dst: XReg, src1: FReg, src2: FReg };
781 flt32 = Flt32 { dst: XReg, src1: FReg, src2: FReg };
785 feq64 = Feq64 { dst: XReg, src1: FReg, src2: FReg };
787 fneq64 = Fneq64 { dst: XReg, src1: FReg, src2: FReg };
[all …]
H A Ddisas.rs239 self.src1.disas(position, disas); in disas()
253 self.src1.disas(position, disas); in disas()
/wasmtime-44.0.1/pulley/tests/all/
H A Dinterp.rs149 src1: x(1), in xadd32()
169 src1: x(1), in xadd64()
194 src1: x(1), in xeq64()
219 src1: x(1), in xneq64()
251 src1: x(1), in xslt64()
283 src1: x(1), in xslteq64()
312 src1: x(1), in xult64()
341 src1: x(1), in xulteq64()
370 src1: x(1), in xeq32()
396 src1: x(1), in xneq32()
[all …]
H A Ddisas.rs46 src1: XReg::x0, in simple()
72 src1: XReg::x0, in no_offsets()
103 src1: XReg::x0, in no_offsets_or_hexdump()
/wasmtime-44.0.1/cranelift/codegen/src/isa/pulley_shared/
H A Dinst.isle116 (IfXeq32 (src1 XReg) (src2 XReg))
117 (IfXneq32 (src1 XReg) (src2 XReg))
118 (IfXslt32 (src1 XReg) (src2 XReg))
119 (IfXslteq32 (src1 XReg) (src2 XReg))
120 (IfXult32 (src1 XReg) (src2 XReg))
123 (IfXeq32I32 (src1 XReg) (src2 i32))
135 (IfXeq64 (src1 XReg) (src2 XReg))
136 (IfXneq64 (src1 XReg) (src2 XReg))
137 (IfXslt64 (src1 XReg) (src2 XReg))
139 (IfXult64 (src1 XReg) (src2 XReg))
[all …]
H A Dlower.isle1388 (rule (emit_cond (Cond.IfXeq32 src1 src2)) (pulley_xeq32 src1 src2))
1389 (rule (emit_cond (Cond.IfXneq32 src1 src2)) (pulley_xneq32 src1 src2))
1390 (rule (emit_cond (Cond.IfXslt32 src1 src2)) (pulley_xslt32 src1 src2))
1391 (rule (emit_cond (Cond.IfXslteq32 src1 src2)) (pulley_xslteq32 src1 src2))
1392 (rule (emit_cond (Cond.IfXult32 src1 src2)) (pulley_xult32 src1 src2))
1393 (rule (emit_cond (Cond.IfXulteq32 src1 src2)) (pulley_xulteq32 src1 src2))
1394 (rule (emit_cond (Cond.IfXeq64 src1 src2)) (pulley_xeq64 src1 src2))
1395 (rule (emit_cond (Cond.IfXneq64 src1 src2)) (pulley_xneq64 src1 src2))
1396 (rule (emit_cond (Cond.IfXslt64 src1 src2)) (pulley_xslt64 src1 src2))
1397 (rule (emit_cond (Cond.IfXslteq64 src1 src2)) (pulley_xslteq64 src1 src2))
[all …]
/wasmtime-44.0.1/cranelift/codegen/meta/src/
H A Dpulley.rs44 src1: &'a str,
67 let src1 = parts.next().unwrap_or(dst); in operands() localVariable
69 Operand::Binop { dst, src1, src2 } in operands()
330 Operand::Binop { dst, src1, src2 } => { in generate_isle()
367 Operand::Binop { dst, src1, src2 } => { in generate_isle()
/wasmtime-44.0.1/cranelift/codegen/src/isa/s390x/
H A Dinst.isle2208 (rule (smul_wide src1 src2)
2215 (rule (umul_wide src1 src2)
4613 (rule (atomic_cas_impl $I32 src1 src2 mem) (atomic_cas32 src1 src2 mem))
4614 (rule (atomic_cas_impl $I64 src1 src2 mem) (atomic_cas64 src1 src2 mem))
4980 (rule (icmps_reg ty src1 src2) (cmp_rr (cmpop_cmps ty) src1 src2))
4983 (rule (icmps_reg_sext32 ty src1 src2) (cmp_rr (cmpop_cmps_sext32 ty) src1 src2))
5015 (rule (icmpu_reg ty src1 src2) (cmp_rr (cmpop_cmpu ty) src1 src2))
5018 (rule (icmpu_reg_zext32 ty src1 src2) (cmp_rr (cmpop_cmpu_zext32 ty) src1 src2))
5078 (rule (fcmp_reg $F32 src1 src2) (fpu_cmp32 src1 src2))
5079 (rule (fcmp_reg $F64 src1 src2) (fpu_cmp64 src1 src2))
[all …]
H A Dlower.isle3571 (atomic_cas _ flags @ (bigendian) addr src1 src2)))
3572 (atomic_cas_impl ty (put_in_reg src1) (put_in_reg src2)
3578 (atomic_cas _ flags @ (littleendian) addr src1 src2)))
3579 (bswap_reg ty (atomic_cas_impl ty (bswap_reg ty (put_in_reg src1))
3585 (let ((src1_reg Reg (put_in_reg src1))
3609 (rule (atomic_cas_body ib $I8 _ tmp val src1 src2)
3615 ;; two bytes of "val" and low two bytes of "src1" and "src2".
3616 (rule 1 (atomic_cas_body ib $I16 (bigendian) tmp val src1 src2)
3624 ;; byte-swapping "src1" and "src" ahead of the loop. Note that this is a
3627 (rule (atomic_cas_body ib $I16 (littleendian) tmp val src1 src2)
[all …]
/wasmtime-44.0.1/cranelift/isle/veri/veri_engine/examples/broken/iadd/
H A Dbroken_add_extend.isle57 ;; (rule (alu_rr_extend_reg op ty src1 extended_reg)
60 ;; (alu_rrr_extend op ty src1 src2 extend)))
/wasmtime-44.0.1/winch/codegen/src/
H A Dmasm.rs1772 fn cmp(&mut self, src1: Reg, src2: RegImm, size: OperandSize) -> Result<()>; in cmp()
1793 src1: Reg, in float_cmp_with_set()
2170 fn v128_and(&mut self, src1: Reg, src2: Reg, dst: WritableReg) -> Result<()>; in v128_and()
2176 fn v128_and_not(&mut self, src1: Reg, src2: Reg, dst: WritableReg) -> Result<()>; in v128_and_not()
2180 fn v128_or(&mut self, src1: Reg, src2: Reg, dst: WritableReg) -> Result<()>; in v128_or()
2184 fn v128_xor(&mut self, src1: Reg, src2: Reg, dst: WritableReg) -> Result<()>; in v128_xor()
2190 fn v128_bitselect(&mut self, src1: Reg, src2: Reg, mask: Reg, dst: WritableReg) -> Result<()>; in v128_bitselect()
2202 src1: Reg, in v128_narrow()
2281 fn v128_min(&mut self, src1: Reg, src2: Reg, dst: WritableReg, kind: V128MinKind) in v128_min()
2285 fn v128_max(&mut self, src1: Reg, src2: Reg, dst: WritableReg, kind: V128MaxKind) in v128_max()
H A Dvisitor.rs900 &mut |masm: &mut M, dst, src1, src2, size| { in visit_f32_eq()
910 &mut |masm: &mut M, dst, src1, src2, size| { in visit_f64_eq()
920 &mut |masm: &mut M, dst, src1, src2, size| { in visit_f32_ne()
930 &mut |masm: &mut M, dst, src1, src2, size| { in visit_f64_ne()
940 &mut |masm: &mut M, dst, src1, src2, size| { in visit_f32_lt()
950 &mut |masm: &mut M, dst, src1, src2, size| { in visit_f64_lt()
960 &mut |masm: &mut M, dst, src1, src2, size| { in visit_f32_gt()
970 &mut |masm: &mut M, dst, src1, src2, size| { in visit_f64_gt()
980 &mut |masm: &mut M, dst, src1, src2, size| { in visit_f32_le()
990 &mut |masm: &mut M, dst, src1, src2, size| { in visit_f64_le()
[all …]
/wasmtime-44.0.1/cranelift/codegen/src/isa/x64/lower/
H A Disle.rs1120 fn x64_mulxl_rvm_hi(&mut self, src1: &GprMem, src2: Gpr) -> Gpr { in x64_mulxl_rvm_hi()
1122 let src1 = self.convert_gpr_mem_to_assembler_read_gpr_mem(src1); in x64_mulxl_rvm_hi() localVariable
1123 let inst = asm::inst::mulxl_rvm::new(ret, ret, src1, src2); in x64_mulxl_rvm_hi()
1128 fn x64_mulxq_rvm_hi(&mut self, src1: &GprMem, src2: Gpr) -> Gpr { in x64_mulxq_rvm_hi()
1130 let src1 = self.convert_gpr_mem_to_assembler_read_gpr_mem(src1); in x64_mulxq_rvm_hi() localVariable
1131 let inst = asm::inst::mulxq_rvm::new(ret, ret, src1, src2); in x64_mulxq_rvm_hi()
/wasmtime-44.0.1/cranelift/codegen/src/isa/aarch64/
H A Dinst.isle2128 (rule (alu_rrr op ty src1 src2)
2251 src1 src2 shift)))
2260 src1 src2 shift)))
2341 (rule (cmn_imm size src1 src2)
2344 src1 src2)))
2351 (rule (cmp size src1 src2)
2354 src1 src2)))
2360 (rule (cmp_imm size src1 src2)
2363 src1 src2)))
2366 (rule (cmp64_imm src1 src2)
[all …]
/wasmtime-44.0.1/winch/codegen/src/isa/aarch64/
H A Dmasm.rs1053 fn cmp(&mut self, src1: Reg, src2: RegImm, size: OperandSize) -> Result<()> { in cmp()
1056 self.asm.subs_rrr(src2, src1, size); in cmp()
1062 Some(imm12) => self.asm.subs_ir(imm12, src1, size), in cmp()
1066 masm.asm.subs_rrr(scratch.inner(), src1, size); in cmp()
1078 src1: Reg, in float_cmp_with_set()
1083 self.asm.fcmp(src1, src2, size); in float_cmp_with_set()
/wasmtime-44.0.1/winch/codegen/src/codegen/
H A Dcontext.rs375 let src1 = self.pop_to_reg(masm, None)?; in float_cmp_op() localVariable
377 emit(masm, dst, src1.reg, src2.reg, size)?; in float_cmp_op()
378 self.free_reg(src1); in float_cmp_op()
/wasmtime-44.0.1/cranelift/codegen/src/isa/x64/inst/
H A Dmod.rs239 pub(crate) fn cmp_mi_sxb(size: OperandSize, src1: Gpr, src2: i8) -> Inst { in cmp_mi_sxb()
241 OperandSize::Size8 => asm::inst::cmpb_mi::new(src1, src2.cast_unsigned()).into(), in cmp_mi_sxb()
242 OperandSize::Size16 => asm::inst::cmpw_mi_sxb::new(src1, src2).into(), in cmp_mi_sxb()
243 OperandSize::Size32 => asm::inst::cmpl_mi_sxb::new(src1, src2).into(), in cmp_mi_sxb()
244 OperandSize::Size64 => asm::inst::cmpq_mi_sxb::new(src1, src2).into(), in cmp_mi_sxb()
/wasmtime-44.0.1/pulley/
H A DCONTRIBUTING.md69 /// `dst = src1 / src2` (signed)
111 let a = self.state[operands.src1].get_i32();
/wasmtime-44.0.1/cranelift/assembler-x64/src/
H A Dcustom.rs672 src1: &mut GprMem<R::ReadGpr, R::ReadGpr>,
683 visitor.read_gpr_mem(src1);

12