| /wasmtime-44.0.1/winch/codegen/src/codegen/ |
| H A D | context.rs | 15 regalloc::RegAlloc,
38 pub regalloc: RegAlloc, field
114 regalloc: RegAlloc, in new()
120 regalloc, in new()
131 regalloc: self.regalloc, in for_emission()
144 self.regalloc.reg(named, |regalloc| { in reg()
177 self.regalloc.reg_for_class(class, &mut |regalloc| { in reg_for_class()
223 self.regalloc.free(reg); in free_reg()
643 f(&mut self.regalloc, v)? in drop_last()
836 regalloc: &mut RegAlloc, in spill_impl()
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| /wasmtime-44.0.1/winch/codegen/src/isa/aarch64/ |
| H A D | mod.rs | 9 regalloc::RegAlloc,
115 let regalloc = RegAlloc::from(gpr_bit_set(), fpr_bit_set()); in compile_function() localVariable
116 let codegen_context = CodeGenContext::new(regalloc, stack, frame, &vmoffsets); in compile_function()
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| /wasmtime-44.0.1/winch/codegen/src/isa/x64/ |
| H A D | mod.rs | 5 use crate::regalloc::RegAlloc;
120 let regalloc = RegAlloc::from(gpr_bit_set(), fpr_bit_set()); in compile_function() localVariable
121 let codegen_context = CodeGenContext::new(regalloc, stack, frame, &vmoffsets); in compile_function()
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| /wasmtime-44.0.1/cranelift/codegen/src/machinst/ |
| H A D | vcode.rs | 670 regalloc: ®alloc2::Output, in compute_clobbers_and_function_calls()
676 for (_, Edit::Move { to, .. }) in ®alloc.edits { in compute_clobbers_and_function_calls()
684 let allocs = ®alloc.allocs[range]; in compute_clobbers_and_function_calls()
738 regalloc: ®alloc2::Output, in emit()
783 regalloc.num_spillslots, in emit()
809 while edit_idx < regalloc.edits.len() && regalloc.edits[edit_idx].0.inst() < end_inst { in emit()
890 for inst_or_edit in regalloc.block_insts_and_edits(&self, block) { in emit()
1214 regalloc: ®alloc2::Output, in compute_value_labels_ranges()
1223 self.log_value_labels_ranges(regalloc, inst_offsets); in compute_value_labels_ranges()
1227 for &(label, from, to, alloc) in ®alloc.debug_locations { in compute_value_labels_ranges()
[all …]
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| H A D | compile.rs | 52 let _tt = timing::regalloc(); in compile()
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| /wasmtime-44.0.1/winch/codegen/src/ |
| H A D | lib.rs | 21 mod regalloc; module
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| H A D | visitor.rs | 2201 self.context.drop_last(1, |regalloc, val| match val { in visit_drop()
2202 Val::Reg(tr) => Ok(regalloc.free(tr.reg)), in visit_drop()
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| /wasmtime-44.0.1/cranelift/codegen/src/ |
| H A D | timing.rs | 72 regalloc: "Register allocation",
334 assert_eq!(Pass::regalloc.to_string(), "Register allocation"); in display()
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| /wasmtime-44.0.1/cranelift/filetests/filetests/isa/aarch64/ |
| H A D | atomic-cas.clif | 1 ; Regression test for incorrect regalloc constraints introduced in #4830
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| /wasmtime-44.0.1/cranelift/filetests/filetests/isa/riscv64/ |
| H A D | bitops-float.clif | 8 ;; causing a regalloc panic.
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| /wasmtime-44.0.1/tests/disas/pulley/ |
| H A D | coremark-1.wat | 7 ;; This doesn't reproduce the exact regalloc decisions but does currently show
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| /wasmtime-44.0.1/cranelift/filetests/filetests/isa/x64/ |
| H A D | fastcall.clif | 166 ;; This is truly odd (because of the regalloc ordering), but it works. Note
168 ;; the regalloc order is optimized for SysV. Also note that because we copy args
174 ;; TODO(#2704): fix regalloc's register priority ordering!
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| /wasmtime-44.0.1/cranelift/docs/ |
| H A D | testing.md | 222 ### `test regalloc`
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| /wasmtime-44.0.1/cranelift/codegen/src/isa/aarch64/ |
| H A D | inst.isle | 189 ;; register, with a regalloc constraint to tie them together.
247 ;; no way to explain to the regalloc about earlyclobber registers, this instruction has
301 ;; them here to have separate use and def vregs for regalloc.
1005 ;; Note that this is emitted post-regalloc so `start` and `end` can be
1162 ;; Specialized here to SP so we don't have to emit regalloc metadata.
1168 ;; Specialized here to SP so we don't have to emit regalloc metadata.
5103 ;; we cannot allow regalloc to insert any spills/fills
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| /wasmtime-44.0.1/cranelift/codegen/src/isa/x64/ |
| H A D | inst.isle | 2026 ;; in regalloc since nothing is constrained. Note that the `shlx` instruction
3362 ;; This must be *one* instruction in the vcode because we cannot allow regalloc
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| /wasmtime-44.0.1/cranelift/codegen/src/isa/riscv64/ |
| H A D | inst.isle | 1874 ;; TODO: Loading the zero reg directly causes a bunch of regalloc errors, we should look into it.
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| H A D | lower.isle | 1927 ;; of the iconst rule because that runs into regalloc issues. gen_select_xreg
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| /wasmtime-44.0.1/cranelift/codegen/src/isa/s390x/ |
| H A D | inst.isle | 31 ;; allocation during regalloc. Hence, we have SSA form here (ri
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| H A D | lower.isle | 4202 ;; we cannot allow regalloc to insert any spills/fills
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