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Searched refs:opcodes (Results 1 – 16 of 16) sorted by relevance

/wasmtime-44.0.1/cranelift/assembler-x64/meta/src/generate/
H A Dformat.rs107 if !rex.opcodes.prefixes.is_empty() { in generate_prefixes()
111 if let Some(group1) = &rex.opcodes.prefixes.group1 { in generate_prefixes()
114 if let Some(group2) = &rex.opcodes.prefixes.group2 { in generate_prefixes()
117 if let Some(group3) = &rex.opcodes.prefixes.group3 { in generate_prefixes()
120 if let Some(group4) = &rex.opcodes.prefixes.group4 { in generate_prefixes()
515 if self.opcodes.escape { in generate_opcodes()
522 fmtln!(f, "buf.put1(0x{:x} | low_bits);", self.opcodes.primary); in generate_opcodes()
524 fmtln!(f, "buf.put1(0x{:x});", self.opcodes.primary); in generate_opcodes()
526 if let Some(secondary) = self.opcodes.secondary { in generate_opcodes()
/wasmtime-44.0.1/docs/
H A Dexamples-pulley.md99 By default all Pulley opcodes are enabled in the interpreter meaning it's
101 includes, for example, SIMD opcodes for all of the WebAssembly SIMD proposal.
102 Not all WebAssembly modules use these opcodes though nor do all embeddings want
104 compile time to compile-out the SIMD opcodes:
111 SIMD opcodes. Instead attempting to execute any opcode will raise a "disabled
138 Pulley opcodes are a single discriminator byte followed by any immediates.
140 Pulley has more than 256 opcodes, however, which is where "extended" opcodes
142 opcode is being used. Extended opcodes follow this initial discriminator with a
163 between opcodes continues with tail-calls and exiting the interpreter is done
203 * When profiling with the "tail loop" you can see hot opcodes much more clearly,
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H A Dexamples-deterministic-wasm-execution.md18 Some Wasm opcodes can result in `NaN` (not-a-number) values. The IEEE-754 spec
H A Dstability-tiers.md346 new table opcodes in the [`reference-types`] proposal.
/wasmtime-44.0.1/cranelift/assembler-x64/meta/src/dsl/
H A Dencoding.rs25 opcodes: opcode.into(), in rex()
84 Encoding::Rex(rex) => rex.opcodes.opcode(), in opcode()
165 pub opcodes: Opcodes, field
355 self.opcodes.primary & 0b111 == 0, in validate()
378 if let Some(group1) = &self.opcodes.prefixes.group1 { in fmt()
381 if let Some(group2) = &self.opcodes.prefixes.group2 { in fmt()
384 if let Some(group3) = &self.opcodes.prefixes.group3 { in fmt()
387 if let Some(group4) = &self.opcodes.prefixes.group4 { in fmt()
393 if self.opcodes.escape { in fmt()
396 write!(f, "{:#04X}", self.opcodes.primary)?; in fmt()
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/wasmtime-44.0.1/cranelift/docs/
H A Dcompare-llvm.md42 opcodes. These main passes are run on the SelectionDAG representation:
46 - Operation legalization eliminates all opcodes that can't be mapped to
74 SelectionDAG representation with ISA-agnostic opcodes on the MachineInstr
86 - Cranelift's opcodes are ISA-agnostic, but after legalization / instruction
172 is emitted, there are opcodes for every native instruction that can be
/wasmtime-44.0.1/tests/disas/pulley/
H A Dcoremark-1.wat15 ;; Ideally to minimize Pulley opcodes this would skip the `xmov` and `jump`
/wasmtime-44.0.1/cranelift/isle/veri/veri_engine/examples/broken/iadd/
H A Dbroken_add_extend.isle62 ;; Only including the i8 to i32 opcodes, based on the impl of extended_value_from_value
/wasmtime-44.0.1/pulley/
H A DREADME.md92 * We do not, in general, define sub-opcodes. There should be only one branch, on
/wasmtime-44.0.1/fuzz/
H A DREADME.md122 …ishl cargo fuzz run cranelift-fuzzgen` will run fuzzgen but only generate `ineg` or `ishl` opcodes.
/wasmtime-44.0.1/cranelift/fuzzgen/src/
H A Dfunction_generator.rs1071 .map_or(true, |opcodes| opcodes.contains(op))
/wasmtime-44.0.1/cranelift/codegen/src/ir/
H A Dinstructions.rs1169 fn opcodes() { in opcodes() function
/wasmtime-44.0.1/cranelift/codegen/src/isa/pulley_shared/
H A Dlower.isle799 ;; opcodes this is an adaptation of riscv64's lowering rules for 128-bit
801 ;; possible to add new opcodes to pulley for 128-bit comparisons.
/wasmtime-44.0.1/cranelift/codegen/src/isa/x64/
H A Dinst.isle1229 ;; opcodes on 32-bits will zero-extend the upper 32-bits, so we can
H A Dlower.isle3146 ;; Explicit 8/16/32-bit opcodes.
/wasmtime-44.0.1/cranelift/codegen/src/isa/aarch64/
H A Dinst.isle1993 ;; Only including the i8 to i32 opcodes, based on the impl of extended_value_from_value