Home
last modified time | relevance | path

Searched refs:decl (Results 1 – 25 of 116) sorted by relevance

12345

/wasmtime-44.0.1/cranelift/codegen/src/
H A Dprelude.isle13 (decl pure unit () Unit)
45 (decl def_inst (Inst) Value)
53 (decl value_type (Type) Value)
57 (decl u32_nonnegative (u32) u32)
62 (decl offset32 (i32) Offset32)
377 (decl ty_16 (Type) Type)
381 (decl ty_32 (Type) Type)
385 (decl ty_64 (Type) Type)
389 (decl ty_128 (Type) Type)
430 (decl ty_int (Type) Type)
[all …]
H A Dprelude_lower.isle39 (decl value_reg (Reg) ValueRegs)
97 (decl temp_reg (Type) Reg)
101 (decl is_valid_reg (bool) Reg)
105 (decl invalid_reg () Reg)
110 (decl valid_reg (Reg) Reg)
125 (decl put_in_reg (Value) Reg)
157 (decl lo_reg (Value) Reg)
163 (decl preg_to_reg (PReg) Reg)
341 (decl uimm8 (u8) Imm64)
385 (decl emit (MInst) Unit)
[all …]
H A Dprelude_opt.isle12 (decl inst_data (InstructionData) Inst)
61 (decl multi simplify (Value) Value)
113 (decl remat (Value) Value)
120 (decl subsume (Value) Value)
189 (decl eq (Type Value Value) Value)
192 (decl ne (Type Value Value) Value)
195 (decl ult (Type Value Value) Value)
198 (decl ule (Type Value Value) Value)
201 (decl ugt (Type Value Value) Value)
204 (decl uge (Type Value Value) Value)
[all …]
/wasmtime-44.0.1/cranelift/codegen/src/isa/s390x/
H A Dinst.isle1638 (decl zero_reg () Reg)
1690 (decl u8_pair (u8 u8) u16)
1812 (decl amt_vr (Value) Reg)
1838 (decl signed () IntCC)
1841 (decl unsigned () IntCC)
2410 (decl load_ar (u8) Reg)
2970 (decl preg_stack () PReg)
2973 (decl preg_gpr_0 () PReg)
2977 (decl sp () Reg)
3752 (decl clz_reg (Reg) Reg)
[all …]
/wasmtime-44.0.1/cranelift/codegen/src/isa/riscv64/
H A Dinst.isle825 (decl xreg_new (Reg) XReg)
1008 (decl pure has_m () bool)
1011 (decl pure has_v () bool)
1099 (decl rv_neg (XReg) XReg)
1165 (decl rv_not (XReg) XReg)
2234 (decl zext (Value) XReg)
2275 (decl sext (Value) XReg)
2999 (decl load_ra () Reg)
3186 (decl fp_reg () PReg)
3189 (decl sp_reg () PReg)
[all …]
H A Dinst_vector.isle84 (decl pure masked (VReg) VecOpMasking)
87 (decl pure unmasked () VecOpMasking)
326 (decl pure vstate_mf2 (VState) VState)
350 (decl pure min_vec_reg_size () u64)
1109 (decl rv_vmv_xs (VReg VState) XReg)
1116 (decl rv_vfmv_fs (VReg VState) FReg)
1123 (decl rv_vmv_sx (XReg VState) VReg)
1137 (decl rv_vmv_vx (XReg VState) VReg)
1151 (decl rv_vmv_vi (Imm5 VState) VReg)
1532 (decl gen_vec_mask (u64) VReg)
[all …]
/wasmtime-44.0.1/cranelift/codegen/src/isa/x64/
H A Dinst.isle662 (decl cc_invert (CC) CC)
666 (decl cc_nz_or_z (CC) CC)
815 (decl xmm_new (Reg) Xmm)
821 (decl gpr_new (Reg) Gpr)
925 (decl lo_gpr (Value) Gpr)
983 (decl is_xmm (Xmm) XmmMem)
3486 (decl bt_imm (u8) u64)
4075 (decl preg_rbp () PReg)
4078 (decl preg_rsp () PReg)
4084 (decl x64_rbp () Reg)
[all …]
/wasmtime-44.0.1/cranelift/isle/isle/isle_examples/run/
H A Dlet_shadowing.isle1 (decl foo (u64) u64)
5 (decl test1 (u64) u64)
11 (decl test2 (u64) u64)
17 (decl test3 (u64) u64)
23 (decl test4 (u64) u64)
30 (decl test5 (u64) u64)
34 (decl test6 (u64) u64)
/wasmtime-44.0.1/cranelift/codegen/src/isa/pulley_shared/
H A Dinst.isle155 (decl cond_invert (Cond) Cond)
449 (decl xreg_new (Reg) XReg)
463 (decl put_in_xreg (Value) XReg)
509 (decl freg_new (Reg) FReg)
569 (decl vreg_new (Reg) VReg)
629 (decl imm (i64) Reg)
648 (decl sp_reg () XReg)
765 (decl zext32 (Value) XReg)
772 (decl sext32 (Value) XReg)
779 (decl zext64 (Value) XReg)
[all …]
/wasmtime-44.0.1/cranelift/isle/veri/veri_engine/examples/broken/
H A Dbroken_fits_in_16_rotl_to_rotr.isle6 (decl lower (Inst) InstOutput)
9 (decl sub (Type Reg Reg) Reg)
13 (decl zero_reg () Reg)
21 (decl extend (Reg bool u8 u8) Reg)
44 (decl put_in_reg_zext32 (Value) Reg)
53 (decl rotr_mask (Type) ImmLogic)
67 (decl sub_imm (Type Reg Imm12) Reg)
71 (decl u8_into_imm12 (u8) Imm12)
80 (decl lsr (Type Reg Reg) Reg)
89 (decl lsl (Type Reg Reg) Reg)
[all …]
H A Dbroken_fits_in_16_with_imm_rotl_to_rotr.isle7 (decl lower (Inst) InstOutput)
10 (decl sub (Type Reg Reg) Reg)
15 (decl zero_reg () Reg)
23 (decl extend (Reg bool u8 u8) Reg)
36 (decl and_imm (Type Reg ImmLogic) Reg)
46 (decl put_in_reg_zext32 (Value) Reg)
59 (decl sub_imm (Type Reg Imm12) Reg)
63 (decl u8_into_imm12 (u8) Imm12)
72 (decl lsr (Type Reg Reg) Reg)
81 (decl lsl (Type Reg Reg) Reg)
[all …]
H A Dbroken_mask_small_rotr.isle5 (decl sub (Type Reg Reg) Reg)
10 (decl zero_reg () Reg)
18 (decl extend (Reg bool u8 u8) Reg)
31 (decl and_imm (Type Reg ImmLogic) Reg)
41 (decl put_in_reg_zext32 (Value) Reg)
51 (decl rotr_mask (Type) ImmLogic)
64 (decl sub_imm (Type Reg Imm12) Reg)
68 (decl u8_into_imm12 (u8) Imm12)
77 (decl lsr (Type Reg Reg) Reg)
86 (decl lsl (Type Reg Reg) Reg)
[all …]
H A Dbroken_rule_or_small_rotr.isle5 (decl sub (Type Reg Reg) Reg)
10 (decl zero_reg () Reg)
18 (decl extend (Reg bool u8 u8) Reg)
41 (decl put_in_reg_zext32 (Value) Reg)
50 (decl rotr_mask (Type) ImmLogic)
64 (decl sub_imm (Type Reg Imm12) Reg)
68 (decl u8_into_imm12 (u8) Imm12)
77 (decl lsr (Type Reg Reg) Reg)
86 (decl lsl (Type Reg Reg) Reg)
95 (decl orr (Type Reg Reg) Reg)
[all …]
/wasmtime-44.0.1/cranelift/isle/isle/isle_examples/pass/
H A Dtest4.isle3 (decl Ext1 (u32) A)
4 (decl Ext2 (u32) A)
11 (decl C (bool) A)
14 (decl Lower (A) A)
26 (decl Lower2 (Opcode) MachInst)
37 (decl F (Opcode) u32)
H A Dprio_trie_bug.isle13 (decl iadd (Value Value) Value)
15 (decl ishl (Value Value) Value)
17 (decl uextend (Value) Value)
19 (decl sextend (Value) Value)
21 (decl iconst (u32) Value)
24 (decl put_in_reg (Value) Reg)
28 (decl invalid_reg () Reg)
30 (decl valid_reg () Reg)
33 (decl pure u32_lteq (u32 u32) Unit)
39 (decl x64_add (Reg Reg) Reg)
[all …]
/wasmtime-44.0.1/cranelift/jit/src/
H A Dbackend.rs222 (&decl.name, decl.linkage) in get_address()
231 (&decl.name, decl.linkage) in get_address()
321 assert!(decl.linkage.is_definable()); in finalize_definitions()
330 assert!(decl.linkage.is_definable()); in finalize_definitions()
469 if !decl.linkage.is_definable() { in define_function_with_control_plane()
471 decl.linkage_name(id).into_owned(), in define_function_with_control_plane()
477 decl.linkage_name(id).into_owned(), in define_function_with_control_plane()
541 if !decl.linkage.is_definable() { in define_function_bytes()
543 decl.linkage_name(id).into_owned(), in define_function_bytes()
576 if !decl.linkage.is_definable() { in define_data()
[all …]
/wasmtime-44.0.1/cranelift/codegen/src/isa/aarch64/
H A Dinst.isle1819 (decl use_lse () Inst)
2033 (decl zero_reg () Reg)
2036 (decl fp_reg () Reg)
2039 (decl stack_reg () Reg)
3086 (decl saddlp8 (Reg) Reg)
3092 (decl uaddlp8 (Reg) Reg)
4290 (decl preg_sp () PReg)
4293 (decl preg_fp () PReg)
4296 (decl preg_link () PReg)
4302 (decl aarch64_sp () Reg)
[all …]
/wasmtime-44.0.1/cranelift/isle/veri/veri_engine/examples/broken/udiv/
H A Dudiv_cve.isle3 (decl lower (Inst) InstOutput)
12 (decl alu_rrr (ALUOp Type Reg Reg) Reg)
22 (decl a64_udiv (Type Reg Reg) Reg)
26 (decl imm (Type u64) Reg)
30 (decl put_in_reg_zext64 (Value) Reg)
37 (decl put_nonzero_in_reg_zext64 (Value) Reg)
/wasmtime-44.0.1/cranelift/isle/isle/isle_examples/fail/
H A Dconverter_extractor_constructor.isle8 (decl t_to_u (T) U)
9 (decl u_to_v (U) V)
10 (decl t_to_v (T) V)
11 (decl v_to_t (V) T)
22 (decl Test1 (U) V)
28 (decl Test2 (U) V)
H A Derror1.isle3 (decl Ext1 (u32) A)
4 (decl Ext2 (u32) A)
8 (decl C (bool) A)
11 (decl Lower (A) A)
25 (decl Lower2 (Opcode) MachInst)
/wasmtime-44.0.1/cranelift/isle/veri/veri_engine/examples/broken/ctz/
H A Dbroken_ctz16.isle3 (decl lower (Inst) InstOutput)
34 (decl operand_size (Type) OperandSize)
38 (decl bit_rr (BitOp Type Reg) Reg)
41 (decl alu_rr_imm_logic (ALUOp Type Reg ImmLogic) Reg)
54 (decl a64_clz (Type Reg) Reg)
67 (decl orr_imm (Type Reg ImmLogic) Reg)
77 (decl rbit (Type Reg) Reg)
83 (decl u64_into_imm_logic (Type u64) ImmLogic)
H A Dbroken_ctz8.isle3 (decl lower (Inst) InstOutput)
34 (decl operand_size (Type) OperandSize)
38 (decl bit_rr (BitOp Type Reg) Reg)
41 (decl alu_rr_imm_logic (ALUOp Type Reg ImmLogic) Reg)
54 (decl a64_clz (Type Reg) Reg)
67 (decl orr_imm (Type Reg ImmLogic) Reg)
77 (decl rbit (Type Reg) Reg)
83 (decl u64_into_imm_logic (Type u64) ImmLogic)
/wasmtime-44.0.1/cranelift/isle/veri/veri_engine/examples/broken/clz/
H A Dbroken_clz16.isle3 (decl lower (Inst) InstOutput)
29 (decl bit_rr (BitOp Type Reg) Reg)
32 (decl alu_rr_imm12 (ALUOp Type Reg Imm12) Reg)
46 (decl sub_imm (Type Reg Imm12) Reg)
56 (decl a64_clz (Type Reg) Reg)
59 (decl extend (Reg bool u8 u8) Reg)
72 (decl put_in_reg_zext32 (Value) Reg)
79 (decl u8_into_imm12 (u8) Imm12)
H A Dbroken_clz8.isle3 (decl lower (Inst) InstOutput)
29 (decl bit_rr (BitOp Type Reg) Reg)
32 (decl alu_rr_imm12 (ALUOp Type Reg Imm12) Reg)
46 (decl sub_imm (Type Reg Imm12) Reg)
56 (decl a64_clz (Type Reg) Reg)
59 (decl extend (Reg bool u8 u8) Reg)
73 (decl put_in_reg_zext32 (Value) Reg)
80 (decl u8_into_imm12 (u8) Imm12)
/wasmtime-44.0.1/cranelift/isle/veri/veri_engine/examples/x86/
H A Damode_add_shl.isle17 (decl iconst (Imm64) Inst)
29 (decl uimm8 (u8) Imm64)
37 (decl pure u8_as_u32 (u8) u32)
41 (decl def_inst (Inst) Value)
46 (decl put_in_reg (Value) Reg)
51 (decl gpr_to_reg (Gpr) Reg)
56 (decl gpr_new (Reg) Gpr)
67 (decl uextend (Value) Inst)
81 (decl ishl (Value Value) Inst)
136 (decl valid_reg (Reg) Reg)
[all …]

12345