Searched refs:allocatable (Results 1 – 5 of 5) sorted by relevance
| /wasmtime-44.0.1/winch/codegen/src/ |
| H A D | regset.rs | 40 allocatable: u64, field
52 pub fn int(allocatable: u64, non_allocatable: u64, max: usize) -> Self { in int()
54 debug_assert!(allocatable & non_allocatable == 0); in int()
57 allocatable, in int()
66 debug_assert!(allocatable & non_allocatable == 0); in float()
69 allocatable, in float()
90 let index = bitset.allocatable.trailing_zeros(); in reg_for_class()
113 self[reg.class()].allocatable |= 1 << index; in free()
123 (!bitset.allocatable & index) == 0 in named_reg_available()
129 bitset.allocatable != 0 in available()
[all …]
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| /wasmtime-44.0.1/cranelift/codegen/src/machinst/ |
| H A D | reg.rs | 378 allocatable: PRegSet, field
385 pub fn new(operands: &'a mut Vec<Operand>, allocatable: PRegSet, renamer: F) -> Self { in new()
389 allocatable, in new()
555 self.allocatable.contains(reg), in debug_assert_is_allocatable_preg()
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| H A D | vcode.rs | 514 let allocatable = PRegSet::from(self.vcode.abi.machine_env()); in collect_operands() localVariable
528 OperandCollector::new(&mut self.vcode.operands, allocatable, |vreg| { in collect_operands()
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| /wasmtime-44.0.1/cranelift/codegen/src/isa/riscv64/ |
| H A D | inst.isle | 173 ;; A MOV instruction, but where the source register is a non-allocatable
174 ;; PReg. It's important that the register be non-allocatable, as regalloc2
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| /wasmtime-44.0.1/cranelift/codegen/src/isa/aarch64/ |
| H A D | inst.isle | 4315 ;; Even though LR is not an allocatable register, whether it
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