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Searched refs:RegClass (Results 1 – 25 of 50) sorted by relevance

12

/wasmtime-44.0.1/winch/codegen/src/
H A Dregset.rs1 use crate::isa::reg::{Reg, RegClass};
13 impl Index<RegClass> for RegSet {
18 RegClass::Int => &self.gpr, in index()
19 RegClass::Float => &self.fpr, in index()
25 impl IndexMut<RegClass> for RegSet {
28 RegClass::Int => &mut self.gpr, in index_mut()
29 RegClass::Float => &mut self.fpr, in index_mut()
38 class: RegClass,
56 class: RegClass::Int, in int()
68 class: RegClass::Float, in float()
[all …]
H A Dregalloc.rs5 isa::reg::{Reg, RegClass},
34 pub fn reg_for_class<F>(&mut self, class: RegClass, spill: &mut F) -> Result<Reg> in reg_for_class() argument
/wasmtime-44.0.1/cranelift/codegen/src/isa/aarch64/inst/
H A Dregs.rs7 use crate::machinst::{Reg, RegClass, Writable};
30 PReg::new(num as usize, RegClass::Int) in xreg_preg()
46 PReg::new(num as usize, RegClass::Float) in vreg_preg()
57 let preg = PReg::new(31, RegClass::Int); in zero_reg()
169 RegClass::Int => show_ireg(rreg), in show_reg()
170 RegClass::Float => show_vreg(rreg), in show_reg()
185 RegClass::Float => show_reg(reg), in show_reg_sized()
186 RegClass::Vector => unreachable!(), in show_reg_sized()
214 if reg.class() != RegClass::Float { in show_vreg_scalar()
236 assert_eq!(RegClass::Float, reg.class()); in show_vreg_vector()
[all …]
/wasmtime-44.0.1/winch/codegen/src/isa/
H A Dreg.rs2 pub use regalloc2::RegClass;
28 pub fn from(class: RegClass, enc: usize) -> Self { in from() argument
39 Self::new(PReg::new(enc, RegClass::Int)) in int()
44 Self::new(PReg::new(enc, RegClass::Float)) in float()
58 pub fn class(&self) -> RegClass { in class() argument
65 self.class() == RegClass::Int in is_int()
70 self.class() == RegClass::Float in is_float()
/wasmtime-44.0.1/cranelift/codegen/src/isa/x64/inst/
H A Dregs.rs12 use regalloc2::{PReg, RegClass, VReg};
18 Reg::from_virtual_reg(VReg::new(preg.index(), RegClass::Int)) in gpr()
21 PReg::new(enc as usize, RegClass::Int) in gpr_preg()
83 Reg::from_virtual_reg(VReg::new(preg.index(), RegClass::Float)) in fpr()
87 PReg::new(enc as usize, RegClass::Float) in fpr_preg()
150 RegClass::Int => { in pretty_print_reg()
160 RegClass::Float => xmm::enc::to_string(enc), in pretty_print_reg()
161 RegClass::Vector => unreachable!(), in pretty_print_reg()
167 if reg.class() == RegClass::Int && size != 8 { in pretty_print_reg()
H A Dexternal.rs10 use regalloc2::{PReg, RegClass};
59 assert!(wgpr.to_reg().class() == RegClass::Int); in from()
68 assert!(gpr.class() == RegClass::Int); in from()
84 assert!(wgpr.to_reg().class() == RegClass::Int); in from()
92 assert!(wgpr.to_reg().class() == RegClass::Int); in from()
148 assert!(wxmm.to_reg().class() == RegClass::Float); in from()
157 assert!(xmm.class() == RegClass::Float); in from()
166 assert!(xmm.class() == RegClass::Float); in from()
333 fn fixed_reg(enc: u8, class: RegClass) -> Reg { in fixed_reg()
531 use regalloc2::{RegClass, VReg};
[all …]
H A Dmod.rs197 src.assert_regclass_is(RegClass::Int); in movzx_rm_r()
277 RegClass::Int => { in load()
306 RegClass::Float => { in load()
337 RegClass::Int => { in store()
347 RegClass::Float => { in store()
1370 RegClass::Int => { in gen_move()
1374 RegClass::Float => { in gen_move()
1420 types::I128 => Ok((&[RegClass::Int, RegClass::Int], &[types::I64, types::I64])), in rc_for_type()
1424 &[RegClass::Float], in rc_for_type()
1437 RegClass::Int => types::I64, in canonical_type_for_rc()
[all …]
/wasmtime-44.0.1/cranelift/codegen/src/isa/x64/inst/unwind/
H A Dwinx64.rs3 use crate::machinst::{Reg, RegClass};
11 RegClass::Int => MappedRegister::Int(reg.to_real_reg().unwrap().hw_enc()), in map()
12 RegClass::Float => MappedRegister::Xmm(reg.to_real_reg().unwrap().hw_enc()), in map()
13 RegClass::Vector => unreachable!(), in map()
H A Dsystemv.rs4 use crate::machinst::{Reg, RegClass};
73 RegClass::Int => { in map_reg()
78 RegClass::Float => Ok(X86_XMM_REG_MAP[reg.to_real_reg().unwrap().hw_enc() as usize]), in map_reg()
79 RegClass::Vector => unreachable!(), in map_reg()
/wasmtime-44.0.1/cranelift/codegen/src/isa/pulley_shared/inst/
H A Dmod.rs15 use regalloc2::RegClass;
427 regalloc2::RegClass::Int => I64, in canonical_type_for_rc()
428 regalloc2::RegClass::Float => F64, in canonical_type_for_rc()
429 regalloc2::RegClass::Vector => I8X16, in canonical_type_for_rc()
550 I8 => Ok((&[RegClass::Int], &[I8])), in rc_for_type()
551 I16 => Ok((&[RegClass::Int], &[I16])), in rc_for_type()
552 I32 => Ok((&[RegClass::Int], &[I32])), in rc_for_type()
553 I64 => Ok((&[RegClass::Int], &[I64])), in rc_for_type()
556 I128 => Ok((&[RegClass::Int, RegClass::Int], &[I64, I64])), in rc_for_type()
574 Ok((&[RegClass::Vector], ty)) in rc_for_type()
[all …]
H A Dregs.rs4 use regalloc2::{PReg, RegClass, VReg};
8 let p = PReg::new(enc, RegClass::Int); in x_reg()
15 PReg::new(enc, RegClass::Int) in px_reg()
20 let p = PReg::new(enc, RegClass::Float); in f_reg()
27 PReg::new(enc, RegClass::Float) in pf_reg()
32 let p = PReg::new(enc, RegClass::Vector); in v_reg()
39 PReg::new(enc, RegClass::Vector) in pv_reg()
/wasmtime-44.0.1/cranelift/codegen/src/isa/riscv64/inst/
H A Dregs.rs6 use regalloc2::{PReg, RegClass, VReg};
133 let p_reg = PReg::new(enc, RegClass::Int); in x_reg()
138 PReg::new(enc, RegClass::Int) in px_reg()
143 let p_reg = PReg::new(enc, RegClass::Float); in f_reg()
148 PReg::new(enc, RegClass::Float) in pf_reg()
152 PReg::new(enc, RegClass::Vector) in pv_reg()
H A Dvector.rs6 use crate::machinst::{OperandVisitor, RegClass};
292 pub fn vs1_regclass(&self) -> RegClass { in vs1_regclass() argument
295 VecOpCategory::OPMVX => RegClass::Int, in vs1_regclass()
296 VecOpCategory::OPFVF => RegClass::Float, in vs1_regclass()
573 pub fn vs1_regclass(&self) -> RegClass { in vs1_regclass() argument
577 VecOpCategory::OPFVF => RegClass::Float, in vs1_regclass()
915 pub fn dst_regclass(&self) -> RegClass { in dst_regclass() argument
936 | VecAluOpRR::VfncvtffW => RegClass::Vector, in dst_regclass()
937 VecAluOpRR::VmvXS => RegClass::Int, in dst_regclass()
938 VecAluOpRR::VfmvFS => RegClass::Float, in dst_regclass()
[all …]
H A Dmod.rs19 use regalloc2::RegClass;
720 regalloc2::RegClass::Int => I64, in canonical_type_for_rc()
721 regalloc2::RegClass::Float => F64, in canonical_type_for_rc()
722 regalloc2::RegClass::Vector => I8X16, in canonical_type_for_rc()
819 I8 => Ok((&[RegClass::Int], &[I8])), in rc_for_type()
820 I16 => Ok((&[RegClass::Int], &[I16])), in rc_for_type()
821 I32 => Ok((&[RegClass::Int], &[I32])), in rc_for_type()
822 I64 => Ok((&[RegClass::Int], &[I64])), in rc_for_type()
827 F128 | I128 => Ok((&[RegClass::Int, RegClass::Int], &[I64, I64])), in rc_for_type()
845 Ok((&[RegClass::Vector], ty)) in rc_for_type()
[all …]
/wasmtime-44.0.1/cranelift/codegen/src/isa/s390x/inst/
H A Dregs.rs19 PReg::new(num as usize, RegClass::Int) in gpr_preg()
34 PReg::new(num as usize, RegClass::Float) in vr_preg()
45 assert!(r.class() == RegClass::Float); in is_fpr()
83 RegClass::Int => format!("%r{}", rreg.hw_enc()), in show_reg()
84 RegClass::Float => format!("%v{}", rreg.hw_enc()), in show_reg()
85 RegClass::Vector => unreachable!(), in show_reg()
/wasmtime-44.0.1/winch/codegen/src/isa/aarch64/
H A Dregs.rs5 use regalloc2::{PReg, RegClass};
15 Reg::new(PReg::new(num as usize, RegClass::Int)) in xreg()
21 Reg::new(PReg::new(num as usize, RegClass::Float)) in vreg()
74 Reg::new(PReg::new(31 + 32, RegClass::Int)) in sp()
/wasmtime-44.0.1/cranelift/codegen/src/isa/aarch64/
H A Dabi.rs49 RegClass::Int => { in compute_clobber_size()
52 RegClass::Float => { in compute_clobber_size()
55 RegClass::Vector => unreachable!(), in compute_clobber_size()
257 rcs == &[RegClass::Int, RegClass::Int], in compute_arg_locs()
1117 rc: RegClass, in get_number_of_spillslots_for_value() argument
1124 RegClass::Int => 1, in get_number_of_spillslots_for_value()
1125 RegClass::Float => vector_size / 8, in get_number_of_spillslots_for_value()
1126 RegClass::Vector => unreachable!(), in get_number_of_spillslots_for_value()
1336 RegClass::Int => { in is_reg_saved_in_prologue()
1347 RegClass::Float => { in is_reg_saved_in_prologue()
[all …]
/wasmtime-44.0.1/cranelift/codegen/src/isa/riscv64/inst/unwind/
H A Dsystemv.rs7 use regalloc2::RegClass;
34 RegClass::Int => 0, in map_reg()
35 RegClass::Float => 32, in map_reg()
36 RegClass::Vector => 64, in map_reg()
/wasmtime-44.0.1/cranelift/codegen/src/isa/unwind/
H A Dwinarm64.rs260 regalloc2::RegClass::Int => { in create_unwind_info_from_insts()
271 regalloc2::RegClass::Float => { in create_unwind_info_from_insts()
282 regalloc2::RegClass::Vector => unreachable!(), in create_unwind_info_from_insts()
290 assert_eq!(reg.class(), regalloc2::RegClass::Int); in create_unwind_info_from_insts()
295 assert_eq!(reg.class(), regalloc2::RegClass::Float); in create_unwind_info_from_insts()
/wasmtime-44.0.1/cranelift/codegen/src/isa/riscv64/
H A Dabi.rs495 RegClass::Int => I64,
496 RegClass::Float => F64,
538 RegClass::Int => I64,
539 RegClass::Float => F64,
540 RegClass::Vector => I8X16,
602 rc: RegClass, in get_number_of_spillslots_for_value() argument
608 RegClass::Int => 1, in get_number_of_spillslots_for_value()
609 RegClass::Float => 1, in get_number_of_spillslots_for_value()
770 RegClass::Int => { in compute_clobber_size()
773 RegClass::Float => { in compute_clobber_size()
[all …]
/wasmtime-44.0.1/cranelift/codegen/src/isa/aarch64/inst/unwind/
H A Dsystemv.rs5 use crate::machinst::{Reg, RegClass};
38 RegClass::Int => { in map_reg()
42 RegClass::Float => { in map_reg()
46 RegClass::Vector => unreachable!(), in map_reg()
/wasmtime-44.0.1/cranelift/codegen/src/isa/s390x/inst/unwind/
H A Dsystemv.rs4 use crate::machinst::{Reg, RegClass};
84 RegClass::Int => Ok(GPR_MAP[reg.to_real_reg().unwrap().hw_enc() as usize]), in map_reg()
85 RegClass::Float => Ok(VR_MAP[reg.to_real_reg().unwrap().hw_enc() as usize]), in map_reg()
86 RegClass::Vector => unreachable!(), in map_reg()
/wasmtime-44.0.1/cranelift/codegen/src/isa/x64/
H A Dabi.rs734 RegClass::Int => types::I64,
778 RegClass::Int => types::I64,
863 rc: RegClass, in get_number_of_spillslots_for_value() argument
869 RegClass::Int => 1, in get_number_of_spillslots_for_value()
1136 RegClass::Int => match r.hw_enc() { in is_callee_save_systemv()
1144 RegClass::Float => false, in is_callee_save_systemv()
1145 RegClass::Vector => unreachable!(), in is_callee_save_systemv()
1154 RegClass::Int => match r.hw_enc() { in is_callee_save_fastcall()
1164 RegClass::Vector => unreachable!(), in is_callee_save_fastcall()
1172 RegClass::Int => { in compute_clobber_size()
[all …]
/wasmtime-44.0.1/cranelift/codegen/src/isa/pulley_shared/
H A Dabi.rs102 } else if (next_f_reg <= f_end) && *rc == RegClass::Float { in compute_arg_locs()
463 rc: RegClass, in get_number_of_spillslots_for_value() argument
476 RegClass::Int | RegClass::Float => slots_for_8bytes, in get_number_of_spillslots_for_value()
478 RegClass::Vector => 2 * slots_for_8bytes, in get_number_of_spillslots_for_value()
693 if r_reg.class() == RegClass::Int { in clobbered_xregs_saved_by_pulley()
725 RegClass::Int => { in manually_managed_clobbers()
739 RegClass::Float => F64, in manually_managed_clobbers()
740 RegClass::Vector => I8X16, in manually_managed_clobbers()
773 RegClass::Int => { in compute_clobber_size()
776 RegClass::Float => { in compute_clobber_size()
[all …]
/wasmtime-44.0.1/cranelift/assembler-x64/meta/src/dsl/
H A Dformat.rs281 pub enum RegClass { enum
286 impl core::fmt::Display for RegClass { implementation
289 RegClass::Gpr => write!(f, "Gpr"), in fmt()
290 RegClass::Xmm => write!(f, "Xmm"), in fmt()
415 pub fn reg_class(&self) -> Option<RegClass> { in reg_class() argument
420 | r32b | r64 | r64a | r64b | rm8 | rm16 | rm32 | rm64 => Some(RegClass::Gpr), in reg_class()
422 Some(RegClass::Xmm) in reg_class()

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