Home
last modified time | relevance | path

Searched refs:Int (Results 1 – 25 of 75) sorted by relevance

123

/wasmtime-44.0.1/cranelift/codegen/meta/src/cdsl/
H A Dtypes.rs116 Int(shared_types::Int), enumerator
167 LaneType::Int(shared_types::Int::I8) => 4, in number()
168 LaneType::Int(shared_types::Int::I16) => 5, in number()
169 LaneType::Int(shared_types::Int::I32) => 6, in number()
170 LaneType::Int(shared_types::Int::I64) => 7, in number()
171 LaneType::Int(shared_types::Int::I128) => 8, in number()
180 LaneType::Int(match num_bits { in int_from_bits()
181 8 => shared_types::Int::I8, in int_from_bits()
182 16 => shared_types::Int::I16, in int_from_bits()
183 32 => shared_types::Int::I32, in int_from_bits()
[all …]
/wasmtime-44.0.1/cranelift/codegen/meta/src/shared/
H A Dtypes.rs4 pub(crate) enum Int { enum
29 type Item = Int;
32 0 => Some(Int::I8), in next()
33 1 => Some(Int::I16), in next()
34 2 => Some(Int::I32), in next()
35 3 => Some(Int::I64), in next()
36 4 => Some(Int::I128), in next()
86 assert_eq!(int_iter.next(), Some(Int::I8)); in int_iter_works()
87 assert_eq!(int_iter.next(), Some(Int::I16)); in int_iter_works()
88 assert_eq!(int_iter.next(), Some(Int::I32)); in int_iter_works()
[all …]
H A Dinstructions.rs521 let Int = &TypeVar::new( in define_simd_arithmetic() localVariable
538 .operands_in(vec![Operand::new("x", Int), Operand::new("y", Int)]) in define_simd_arithmetic()
550 .operands_in(vec![Operand::new("x", Int), Operand::new("y", Int)]) in define_simd_arithmetic()
562 .operands_in(vec![Operand::new("x", Int), Operand::new("y", Int)]) in define_simd_arithmetic()
574 .operands_in(vec![Operand::new("x", Int), Operand::new("y", Int)]) in define_simd_arithmetic()
689 let Int = &TypeVar::new( in define() localVariable
1805 .operands_in(vec![Operand::new("x", Int), Operand::new("y", Int)]) in define()
1820 .operands_in(vec![Operand::new("x", Int), Operand::new("y", Int)]) in define()
1861 .operands_in(vec![Operand::new("x", Int), Operand::new("y", Int)]) in define()
1876 .operands_in(vec![Operand::new("x", Int), Operand::new("y", Int)]) in define()
[all …]
/wasmtime-44.0.1/cranelift/isle/isle/src/
H A Dlexer.rs58 Int(i128), enumerator
242 let tok = Token::Int(num); in next_token()
286 matches!(self, Token::Int(_)) in is_int()
320 Token::Int(23), in lexer_basic()
321 Token::Int(-568), in lexer_basic()
334 assert_eq!(lex("23"), [Token::Int(23)]); in ends_with_num()
357 [Token::Int(0), Token::Int(1), Token::Int(-1)] in integers()
362 [Token::Int(-1)] in integers()
367 [Token::Int(i128::MAX)] in integers()
H A Dsema.rs91 Int(IntType), enumerator
172 Self::Int(IntType::U8),
173 Self::Int(IntType::U16),
174 Self::Int(IntType::U32),
175 Self::Int(IntType::U64),
176 Self::Int(IntType::U128),
178 Self::Int(IntType::I8),
179 Self::Int(IntType::I16),
180 Self::Int(IntType::I32),
181 Self::Int(IntType::I64),
[all …]
/wasmtime-44.0.1/cranelift/codegen/src/isa/aarch64/inst/
H A Dregs.rs30 PReg::new(num as usize, RegClass::Int) in xreg_preg()
57 let preg = PReg::new(31, RegClass::Int); in zero_reg()
58 Reg::from(VReg::new(preg.index(), RegClass::Int)) in zero_reg()
79 let preg = PReg::new(31 + 32, RegClass::Int); in stack_reg()
80 Reg::from(VReg::new(preg.index(), RegClass::Int)) in stack_reg()
169 RegClass::Int => show_ireg(rreg), in show_reg()
184 RegClass::Int => show_ireg_sized(reg, size), in show_reg_sized()
198 if reg.class() != RegClass::Int || !size.is32() { in show_ireg_sized()
204 if reg.class() == RegClass::Int && size.is32() && s.starts_with("x") { in show_ireg_sized()
/wasmtime-44.0.1/winch/codegen/src/
H A Dregset.rs18 RegClass::Int => &self.gpr, in index()
28 RegClass::Int => &mut self.gpr, in index_mut()
56 class: RegClass::Int, in int()
79 debug_assert!(gpr.class == RegClass::Int); in new()
158 let gpr = set.reg_for_class(RegClass::Int); in test_any_gpr()
162 assert!(!set.available(RegClass::Int)); in test_any_gpr()
163 assert!(set.reg_for_class(RegClass::Int).is_none()) in test_any_gpr()
190 let gpr = set.reg_for_class(RegClass::Int).unwrap(); in test_free_reg()
/wasmtime-44.0.1/cranelift/isle/veri/veri_engine/examples/broken/udiv/
H A Dudiv_cve_underlying.isle14 ((args Int (bv 64)) (ret (bv 64)) (canon (bv 8)))
15 ((args Int (bv 64)) (ret (bv 64)) (canon (bv 16)))
16 ((args Int (bv 64)) (ret (bv 64)) (canon (bv 32)))
17 ((args Int (bv 64)) (ret (bv 64)) (canon (bv 64)))
/wasmtime-44.0.1/cranelift/codegen/src/isa/pulley_shared/inst/
H A Dmod.rs427 regalloc2::RegClass::Int => I64, in canonical_type_for_rc()
550 I8 => Ok((&[RegClass::Int], &[I8])), in rc_for_type()
551 I16 => Ok((&[RegClass::Int], &[I16])), in rc_for_type()
552 I32 => Ok((&[RegClass::Int], &[I32])), in rc_for_type()
553 I64 => Ok((&[RegClass::Int], &[I64])), in rc_for_type()
556 I128 => Ok((&[RegClass::Int, RegClass::Int], &[I64, I64])), in rc_for_type()
595 RegClass::Int in ref_type_regclass()
627 (RegClass::Int, 63) => format!("sp"), in reg_name()
628 (RegClass::Int, 62) => format!("lr"), in reg_name()
629 (RegClass::Int, 61) => format!("fp"), in reg_name()
[all …]
/wasmtime-44.0.1/cranelift/codegen/src/isa/x64/inst/unwind/
H A Dwinx64.rs11 RegClass::Int => MappedRegister::Int(reg.to_real_reg().unwrap().hw_enc()), in map()
/wasmtime-44.0.1/cranelift/codegen/src/isa/x64/inst/
H A Dexternal.rs59 assert!(wgpr.to_reg().class() == RegClass::Int); in from()
68 assert!(gpr.class() == RegClass::Int); in from()
84 assert!(wgpr.to_reg().class() == RegClass::Int); in from()
92 assert!(wgpr.to_reg().class() == RegClass::Int); in from()
283 .reg_fixed_use(reg, fixed_reg(enc, RegClass::Int)); in fixed_read_gpr()
289 .reg_fixed_use(read, fixed_reg(enc, RegClass::Int)); in fixed_read_write_gpr()
291 .reg_fixed_def(write, fixed_reg(enc, RegClass::Int)); in fixed_read_write_gpr()
296 .reg_fixed_def(reg, fixed_reg(enc, RegClass::Int)); in fixed_write_gpr()
540 let v200: Reg = VReg::new(200, RegClass::Int).into(); in pretty_print_registers()
544 let v300: Reg = VReg::new(300, RegClass::Int).into(); in pretty_print_registers()
H A Dregs.rs18 Reg::from_virtual_reg(VReg::new(preg.index(), RegClass::Int)) in gpr()
21 PReg::new(enc as usize, RegClass::Int) in gpr_preg()
150 RegClass::Int => { in pretty_print_reg()
167 if reg.class() == RegClass::Int && size != 8 { in pretty_print_reg()
H A Dmod.rs165 debug_assert!(dst.to_reg().class() == RegClass::Int); in imm()
197 src.assert_regclass_is(RegClass::Int); in movzx_rm_r()
198 debug_assert!(dst.to_reg().class() == RegClass::Int); in movzx_rm_r()
222 src.assert_regclass_is(RegClass::Int); in movsx_rm_r()
258 info.dest.assert_regclass_is(RegClass::Int); in call_unknown()
277 RegClass::Int => { in load()
337 RegClass::Int => { in store()
1370 RegClass::Int => { in gen_move()
1420 types::I128 => Ok((&[RegClass::Int, RegClass::Int], &[types::I64, types::I64])), in rc_for_type()
1437 RegClass::Int => types::I64, in canonical_type_for_rc()
[all …]
H A Dargs.rs303 |reg| reg.class() == RegClass::Int
345 debug_assert!(base.class() == RegClass::Int); in imm_reg()
355 debug_assert!(base.class() == RegClass::Int); in imm_reg_reg_shift()
356 debug_assert!(index.class() == RegClass::Int); in imm_reg_reg_shift()
647 debug_assert!(reg.class() == RegClass::Int || reg.class() == RegClass::Float); in reg()
715 debug_assert!(reg.class() == RegClass::Int || reg.class() == RegClass::Float); in reg()
/wasmtime-44.0.1/cranelift/isle/veri/veri_engine/examples/broken/shifts/
H A Dbroken_ishl_to_do_shift_64.isle99 ((args (bv 8) Int (bv 64) (bv 8)) (ret (bv 64)) (canon (bv 8)))
100 ((args (bv 8) Int (bv 64) (bv 16)) (ret (bv 64)) (canon (bv 16)))
101 ((args (bv 8) Int (bv 64) (bv 32)) (ret (bv 64)) (canon (bv 32)))
102 ((args (bv 8) Int (bv 64) (bv 64)) (ret (bv 64)) (canon (bv 64)))
H A Dbroken_sshr_to_do_shift_fits_in_32.isle88 ((args (bv 8) Int (bv 64) (bv 8)) (ret (bv 64)) (canon (bv 8)))
89 ((args (bv 8) Int (bv 64) (bv 16)) (ret (bv 64)) (canon (bv 16)))
90 ((args (bv 8) Int (bv 64) (bv 32)) (ret (bv 64)) (canon (bv 32)))
91 ((args (bv 8) Int (bv 64) (bv 64)) (ret (bv 64)) (canon (bv 64)))
H A Dbroken_do_shift_32.isle83 ((args (bv 8) Int (bv 64) (bv 8)) (ret (bv 64)) (canon (bv 8)))
84 ((args (bv 8) Int (bv 64) (bv 16)) (ret (bv 64)) (canon (bv 16)))
85 ((args (bv 8) Int (bv 64) (bv 32)) (ret (bv 64)) (canon (bv 32)))
86 ((args (bv 8) Int (bv 64) (bv 64)) (ret (bv 64)) (canon (bv 64)))
H A Dbroken_ushr_to_do_shift_fits_in_32.isle99 ((args (bv 8) Int (bv 64) (bv 8)) (ret (bv 64)) (canon (bv 8)))
100 ((args (bv 8) Int (bv 64) (bv 16)) (ret (bv 64)) (canon (bv 16)))
101 ((args (bv 8) Int (bv 64) (bv 32)) (ret (bv 64)) (canon (bv 32)))
102 ((args (bv 8) Int (bv 64) (bv 64)) (ret (bv 64)) (canon (bv 64)))
/wasmtime-44.0.1/winch/codegen/src/isa/
H A Dreg.rs39 Self::new(PReg::new(enc, RegClass::Int)) in int()
65 self.class() == RegClass::Int in is_int()
/wasmtime-44.0.1/winch/codegen/src/isa/aarch64/
H A Dregs.rs15 Reg::new(PReg::new(num as usize, RegClass::Int)) in xreg()
74 Reg::new(PReg::new(31 + 32, RegClass::Int)) in sp()
/wasmtime-44.0.1/cranelift/codegen/src/isa/riscv64/inst/
H A Dregs.rs133 let p_reg = PReg::new(enc, RegClass::Int); in x_reg()
138 PReg::new(enc, RegClass::Int) in px_reg()
/wasmtime-44.0.1/cranelift/codegen/src/isa/aarch64/
H A Dabi.rs49 RegClass::Int => { in compute_clobber_size()
257 rcs == &[RegClass::Int, RegClass::Int], in compute_arg_locs()
300 RegClass::Int => &mut next_xreg, in compute_arg_locs()
315 RegClass::Int => xreg(*next_reg), in compute_arg_locs()
811 debug_assert_eq!(rd.class(), RegClass::Int);
839 debug_assert!(rt.class() == RegClass::Int);
840 debug_assert!(rt2.class() == RegClass::Int);
1042 debug_assert_eq!(rt.to_reg().class(), RegClass::Int);
1060 debug_assert_eq!(rd.to_reg().class(), RegClass::Int);
1124 RegClass::Int => 1, in get_number_of_spillslots_for_value()
[all …]
/wasmtime-44.0.1/cranelift/codegen/src/isa/s390x/inst/
H A Dregs.rs19 PReg::new(num as usize, RegClass::Int) in gpr_preg()
83 RegClass::Int => format!("%r{}", rreg.hw_enc()), in show_reg()
/wasmtime-44.0.1/cranelift/isle/veri/
H A DREADME.md98 Models can be `Bool`, `Int`, or `(bv)` with or without a specific bitwidth. If the bitwidth is not …
118 The following terms exactly match the [SMT-LIB theories `Int`](https://smt-lib.org/theories-Ints.s…
163 - `zero_ext`: `(zero_ext w e)` where `w : Int` and `e : (bv N)` is equivalent to SMT-LIB `((_ zero_…
164 - `sign_ext`: `(sign_ext w e)` where `w : Int` and `e : (bv N)` is equivalent to SMT-LIB `((_ sign_…
174 - `convto`: `(convto w e)` where `w : Int` and `e : (bv N)` converts the bitvector `e` to the width…
181 - `load_effect`: `(load_effect flags size address)` where `flags : (bv 16)`, `size: Int`, and `addr…
182 - `store_effect`: `(store_effect flags size val address)` where `flags : (bv 16)`, `size: Int`, and…
/wasmtime-44.0.1/crates/wasi-nn/src/backend/
H A Dpytorch.rs267 Kind::Int => Ok(std::mem::size_of::<i32>()), in kind_to_size()
284 TensorType::I32 => Ok(Kind::Int), in try_from()
304 Kind::Int => Ok(TensorType::I32), in try_from()

123