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/oneTBB/examples/graph/logic_sim/
H A DD_latch.hpp28 and_gate<2> second_and; member in D_latch
44 second_and(g), in D_latch()
48 make_edge(D_port, input_port<1>(second_and)); in D_latch()
50 make_edge(E_port, input_port<0>(second_and)); in D_latch()
53 make_edge(second_and, input_port<1>(second_nor)); in D_latch()
63 D_port, E_port, a_not, first_and, second_and, first_nor, second_nor); in D_latch()