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/oneTBB/examples/graph/logic_sim/
H A DD_latch.hpp29 nor_gate<2> first_nor; member in D_latch
45 first_nor(g), in D_latch()
52 make_edge(first_and, input_port<0>(first_nor)); in D_latch()
54 make_edge(first_nor, input_port<0>(second_nor)); in D_latch()
55 make_edge(second_nor, input_port<1>(first_nor)); in D_latch()
58 base_type::output_ports_type output_tuple(output_port<0>(first_nor), in D_latch()
63 D_port, E_port, a_not, first_and, second_and, first_nor, second_nor); in D_latch()