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/oneTBB/examples/graph/logic_sim/
H A DD_latch.hpp26 not_gate a_not; member in D_latch
42 a_not(g), in D_latch()
47 make_edge(D_port, input_port<0>(a_not)); in D_latch()
51 make_edge(a_not, input_port<0>(first_and)); in D_latch()
63 D_port, E_port, a_not, first_and, second_and, first_nor, second_nor); in D_latch()