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Searched refs:S0 (Results 1 – 2 of 2) sorted by relevance

/oneTBB/examples/graph/logic_sim/
H A Done_bit_adder.hpp33 const int S0 = 0; variable
H A Dtest_all.cpp348 make_edge(output_port<P::S0>(my_adder), Sum.get_in()); in main()
513 make_edge(output_port<P::S0>(two_adder), input_port<0>(Sum)); in main()
561 make_edge(output_port<P::S0>(four_adder), input_port<0>(Sum)); in main()