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/oneTBB/examples/graph/logic_sim/
H A Done_bit_adder.hpp57 or_gate<2> FirstOR; member in one_bit_adder
74 FirstOR(g) { in one_bit_adder()
88 FirstOR(src.my_graph) { in one_bit_adder()
105 make_edge(SecondAND, input_port<0>(FirstOR)); in make_connections()
106 make_edge(FirstAND, input_port<1>(FirstOR)); in make_connections()
112 output_port<0>(FirstOR)); in set_up_composite()
115 A_port, B_port, CI_port, FirstXOR, SecondXOR, FirstAND, SecondAND, FirstOR); in set_up_composite()