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/oneTBB/examples/graph/logic_sim/
H A Done_bit_adder.hpp22 const int CI = 0; variable
H A Dtest_all.cpp347 make_edge(CarryIN.get_out(), input_port<P::CI>(my_adder)); in main()
519 make_edge(CarryIN.get_out(), input_port<P::CI>(two_adder)); in main()
575 make_edge(CarryIN.get_out(), input_port<P::CI>(four_adder)); in main()
/oneTBB/
H A DREADME.md2 …img.shields.io/badge/license-Apache_2.0-green.svg)](LICENSE.txt) [![oneTBB CI](https://github.com/…
/oneTBB/.github/workflows/
H A Dci.yml15 name: oneTBB CI