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/oneTBB/examples/graph/logic_sim/
H A Done_bit_adder.hpp26 const int B1 = 4; variable
H A Dtest_all.cpp516 make_edge(B[1].get_out(), input_port<P::B1>(two_adder)); in main()
564 make_edge(B[1].get_out(), input_port<P::B1>(four_adder)); in main()