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Searched refs:B0 (Results 1 – 2 of 2) sorted by relevance

/oneTBB/examples/graph/logic_sim/
H A Done_bit_adder.hpp24 const int B0 = 2; variable
H A Dtest_all.cpp346 make_edge(B.get_out(), input_port<P::B0>(my_adder)); in main()
512 make_edge(B[0].get_out(), input_port<P::B0>(two_adder)); in main()
560 make_edge(B[0].get_out(), input_port<P::B0>(four_adder)); in main()