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/llvm-project-15.0.7/llvm/test/CodeGen/Thumb2/
H A Dmve-vpt-nots.mir65 ; CHECK: MVE_VPTv4s32r 12, renamable $q0, $zr, 11, implicit-def $vpr
71 renamable $vpr = MVE_VCMPs32r renamable $q0, $zr, 11, 0, $noreg, $noreg
92 ; CHECK: BUNDLE implicit-def $vpr, implicit $q0, implicit $zr, implicit $q1 {
93 ; CHECK: MVE_VPTv4s32r 8, renamable $q0, $zr, 11, implicit-def $vpr
108 renamable $vpr = MVE_VCMPs32r renamable $q0, $zr, 11, 0, $noreg, $noreg
135 ; CHECK: MVE_VPTv4s32r 8, renamable $q0, $zr, 11, implicit-def $vpr
146 renamable $vpr = MVE_VCMPs32r renamable $q0, $zr, 11, 0, $noreg, $noreg
170 ; CHECK: MVE_VPTv4s32r 8, renamable $q0, $zr, 11, implicit-def $vpr
184 renamable $vpr = MVE_VCMPs32r renamable $q0, $zr, 11, 0, $noreg, $noreg
219 renamable $vpr = MVE_VCMPs32r renamable $q0, $zr, 11, 0, $noreg, $noreg
[all …]
H A Dmve-pred-vselect.ll7 ; CHECK-NEXT: vpt.i32 eq, q1, zr
8 ; CHECK-NEXT: vcmpt.i32 ne, q2, zr
10 ; CHECK-NEXT: vpt.i32 eq, q0, zr
11 ; CHECK-NEXT: vcmpt.i32 eq, q2, zr
29 ; CHECK-NEXT: vpt.i16 eq, q1, zr
30 ; CHECK-NEXT: vcmpt.i16 ne, q2, zr
32 ; CHECK-NEXT: vpt.i16 eq, q0, zr
33 ; CHECK-NEXT: vcmpt.i16 eq, q2, zr
51 ; CHECK-NEXT: vpt.i8 eq, q1, zr
52 ; CHECK-NEXT: vcmpt.i8 ne, q2, zr
[all …]
H A Dmve-pred-or.ll7 ; CHECK-NEXT: vpt.i32 ne, q0, zr
8 ; CHECK-NEXT: vcmpt.i32 ne, q1, zr
22 ; CHECK-NEXT: vpt.i32 ne, q0, zr
23 ; CHECK-NEXT: vcmpt.i32 eq, q1, zr
37 ; CHECK-NEXT: vpt.i32 ne, q0, zr
38 ; CHECK-NEXT: vcmpt.s32 ge, q1, zr
52 ; CHECK-NEXT: vpt.i32 ne, q0, zr
53 ; CHECK-NEXT: vcmpt.s32 le, q1, zr
67 ; CHECK-NEXT: vpt.i32 ne, q0, zr
82 ; CHECK-NEXT: vpt.i32 ne, q0, zr
[all …]
H A Dmve-pred-selectop.ll7 ; CHECK-NEXT: vpt.i32 eq, q0, zr
20 ; CHECK-NEXT: vpt.i16 eq, q0, zr
33 ; CHECK-NEXT: vpt.i8 eq, q0, zr
46 ; CHECK-NEXT: vpt.i32 eq, q0, zr
59 ; CHECK-NEXT: vpt.i16 eq, q0, zr
72 ; CHECK-NEXT: vpt.i8 eq, q0, zr
85 ; CHECK-NEXT: vpt.i32 eq, q0, zr
98 ; CHECK-NEXT: vpt.i16 eq, q0, zr
111 ; CHECK-NEXT: vpt.i8 eq, q0, zr
150 ; CHECK-NEXT: vpt.i8 eq, q0, zr
[all …]
H A Dmve-pred-xor.ll7 ; CHECK-NEXT: vcmp.i32 eq, q1, zr
9 ; CHECK-NEXT: vcmp.i32 eq, q0, zr
26 ; CHECK-NEXT: vcmp.i32 ne, q1, zr
28 ; CHECK-NEXT: vcmp.i32 eq, q0, zr
45 ; CHECK-NEXT: vcmp.s32 lt, q1, zr
47 ; CHECK-NEXT: vcmp.i32 eq, q0, zr
64 ; CHECK-NEXT: vcmp.s32 gt, q1, zr
66 ; CHECK-NEXT: vcmp.i32 eq, q0, zr
83 ; CHECK-NEXT: vcmp.s32 le, q1, zr
85 ; CHECK-NEXT: vcmp.i32 eq, q0, zr
[all …]
H A Dmve-vcmpz.ll7 ; CHECK-NEXT: vcmp.i32 eq, q0, zr
19 ; CHECK-NEXT: vcmp.i32 ne, q0, zr
31 ; CHECK-NEXT: vcmp.s32 gt, q0, zr
43 ; CHECK-NEXT: vcmp.s32 ge, q0, zr
55 ; CHECK-NEXT: vcmp.s32 lt, q0, zr
67 ; CHECK-NEXT: vcmp.s32 le, q0, zr
79 ; CHECK-NEXT: vcmp.i32 ne, q0, zr
113 ; CHECK-NEXT: vcmp.u32 cs, q0, zr
126 ; CHECK-NEXT: vcmp.i16 eq, q0, zr
138 ; CHECK-NEXT: vcmp.i16 ne, q0, zr
[all …]
H A Dmve-pred-and.ll8 ; CHECK-NEXT: vcmp.i32 eq, q2, zr
22 ; CHECK-NEXT: vpt.i32 eq, q0, zr
23 ; CHECK-NEXT: vcmpt.i32 ne, q1, zr
37 ; CHECK-NEXT: vpt.i32 eq, q0, zr
38 ; CHECK-NEXT: vcmpt.s32 lt, q1, zr
52 ; CHECK-NEXT: vpt.i32 eq, q0, zr
53 ; CHECK-NEXT: vcmpt.s32 gt, q1, zr
67 ; CHECK-NEXT: vpt.i32 eq, q0, zr
82 ; CHECK-NEXT: vpt.i32 eq, q0, zr
110 ; CHECK-NEXT: vpt.i32 eq, q0, zr
[all …]
H A Dmve-pred-not.ll7 ; CHECK-NEXT: vcmp.i32 eq, q0, zr
20 ; CHECK-NEXT: vcmp.i32 eq, q0, zr
33 ; CHECK-NEXT: vcmp.i32 eq, q0, zr
46 ; CHECK-NEXT: vcmp.i32 eq, q0, zr
59 ; CHECK-NEXT: vcmp.i32 eq, q0, zr
72 ; CHECK-NEXT: vcmp.i32 eq, q0, zr
85 ; CHECK-NEXT: vcmp.i32 eq, q0, zr
98 ; CHECK-NEXT: vcmp.i32 eq, q0, zr
111 ; CHECK-NEXT: vcmp.i32 eq, q0, zr
124 ; CHECK-NEXT: vcmp.i32 eq, q0, zr
[all …]
H A Dmve-vecreduce-addpred.ll7 ; CHECK-NEXT: vpt.i32 eq, q1, zr
20 ; CHECK-NEXT: vpt.i32 eq, q1, zr
34 ; CHECK-NEXT: vpt.i32 eq, q1, zr
112 ; CHECK-NEXT: vpt.i16 eq, q1, zr
126 ; CHECK-NEXT: vpt.i16 eq, q1, zr
142 ; CHECK-NEXT: vpt.i32 eq, q1, zr
158 ; CHECK-NEXT: vpt.i32 eq, q1, zr
172 ; CHECK-NEXT: vpt.i16 eq, q1, zr
484 ; CHECK-NEXT: vpt.i8 eq, q1, zr
498 ; CHECK-NEXT: vpt.i8 eq, q1, zr
[all …]
H A Dmve-masked-ldst-offset.ll9 ; CHECK-NEXT: vpt.i32 ne, q0, zr
29 ; CHECK-NEXT: vpt.i32 ne, q0, zr
49 ; CHECK-NEXT: vpt.i32 ne, q0, zr
68 ; CHECK-NEXT: vpt.i32 ne, q0, zr
88 ; CHECK-NEXT: vpt.i32 ne, q0, zr
107 ; CHECK-NEXT: vpt.i32 ne, q0, zr
127 ; CHECK-NEXT: vpt.i32 ne, q0, zr
146 ; CHECK-NEXT: vpt.i32 ne, q0, zr
167 ; CHECK-NEXT: vpt.i32 ne, q0, zr
187 ; CHECK-NEXT: vpt.i32 ne, q0, zr
[all …]
H A Dmve-masked-ldst-preinc.ll9 ; CHECK-NEXT: vpt.i32 ne, q0, zr
29 ; CHECK-NEXT: vpt.i32 ne, q0, zr
49 ; CHECK-NEXT: vpt.i32 ne, q0, zr
68 ; CHECK-NEXT: vpt.i32 ne, q0, zr
88 ; CHECK-NEXT: vpt.i32 ne, q0, zr
107 ; CHECK-NEXT: vpt.i32 ne, q0, zr
127 ; CHECK-NEXT: vpt.i32 ne, q0, zr
146 ; CHECK-NEXT: vpt.i32 ne, q0, zr
167 ; CHECK-NEXT: vpt.i32 ne, q0, zr
187 ; CHECK-NEXT: vpt.i32 ne, q0, zr
[all …]
H A Dmve-masked-ldst-postinc.ll9 ; CHECK-NEXT: vpt.i32 ne, q0, zr
28 ; CHECK-NEXT: vpt.i32 ne, q0, zr
48 ; CHECK-NEXT: vpt.i32 ne, q0, zr
68 ; CHECK-NEXT: vpt.i32 ne, q0, zr
87 ; CHECK-NEXT: vpt.i32 ne, q0, zr
107 ; CHECK-NEXT: vpt.i32 ne, q0, zr
126 ; CHECK-NEXT: vpt.i32 ne, q0, zr
146 ; CHECK-NEXT: vpt.i32 ne, q0, zr
166 ; CHECK-NEXT: vpt.i32 ne, q0, zr
187 ; CHECK-NEXT: vpt.i32 ne, q0, zr
[all …]
H A Dmve-masked-load.ll8 ; CHECK-LE-NEXT: vpt.s32 gt, q0, zr
15 ; CHECK-BE-NEXT: vpt.s32 gt, q1, zr
28 ; CHECK-LE-NEXT: vpt.s32 gt, q0, zr
35 ; CHECK-BE-NEXT: vpt.s32 gt, q1, zr
50 ; CHECK-LE-NEXT: vcmp.s32 gt, q0, zr
90 ; CHECK-BE-NEXT: vcmp.s32 gt, q1, zr
134 ; CHECK-LE-NEXT: vpt.s32 gt, q0, zr
142 ; CHECK-BE-NEXT: vpt.s32 gt, q1, zr
156 ; CHECK-LE-NEXT: vpt.s32 gt, q0, zr
163 ; CHECK-BE-NEXT: vpt.s32 gt, q1, zr
[all …]
H A Dmve-pred-shuffle.ll35 ; CHECK-NEXT: vcmp.i32 eq, q0, zr
60 ; CHECK-NEXT: vcmp.i16 eq, q0, zr
85 ; CHECK-NEXT: vcmp.i8 eq, q0, zr
137 ; CHECK-NEXT: vcmp.i32 eq, q0, zr
158 ; CHECK-NEXT: vcmp.i16 eq, q0, zr
179 ; CHECK-NEXT: vcmp.i8 eq, q0, zr
221 ; CHECK-NEXT: vcmp.i32 eq, q0, zr
275 ; CHECK-NEXT: vcmp.i8 eq, q0, zr
281 ; CHECK-NEXT: vcmp.i8 ne, q0, zr
380 ; CHECK-NEXT: vcmp.i8 eq, q0, zr
[all …]
H A Dmve-vecreduce-mlapred.ll7 ; CHECK-NEXT: vpt.i32 eq, q2, zr
21 ; CHECK-NEXT: vpt.i32 eq, q2, zr
37 ; CHECK-NEXT: vpt.i32 eq, q2, zr
115 ; CHECK-NEXT: vpt.i16 eq, q2, zr
131 ; CHECK-NEXT: vpt.i16 eq, q2, zr
150 ; CHECK-NEXT: vpt.i32 eq, q2, zr
169 ; CHECK-NEXT: vpt.i32 eq, q2, zr
185 ; CHECK-NEXT: vpt.i16 eq, q2, zr
200 ; CHECK-NEXT: vpt.i16 eq, q2, zr
216 ; CHECK-NEXT: vpt.i16 eq, q2, zr
[all …]
H A Dmve-vpsel.ll7 ; CHECK-NEXT: vcmp.i8 ne, q0, zr
19 ; CHECK-NEXT: vcmp.i16 ne, q0, zr
31 ; CHECK-NEXT: vcmp.i32 ne, q0, zr
64 ; CHECK-NEXT: vcmp.i16 ne, q0, zr
76 ; CHECK-NEXT: vcmp.i32 ne, q0, zr
112 ; CHECK-NEXT: vcmp.i32 eq, q2, zr
H A Dconstant-islands-ldrsb.mir30 renamable $r0 = t2CSINC $zr, $zr, 3, implicit killed $cpsr
53 renamable $r0 = t2CSINC $zr, $zr, 3, implicit killed $cpsr
H A Dmve-vpt-block-elses.mir74 …; CHECK: renamable $vpr = MVE_VCMPs32r killed renamable $q0, $zr, 12, 1, internal killed renamab…
75 …; CHECK: renamable $vpr = MVE_VCMPs32r renamable $q1, $zr, 12, 2, internal killed renamable $vpr…
93 …; CHECK: renamable $vpr = MVE_VCMPs32r renamable $q1, $zr, 12, 2, internal killed renamable $vpr…
101 …; CHECK: renamable $vpr = MVE_VCMPs32r renamable $q1, $zr, 12, 2, internal killed renamable $vpr…
127 …; CHECK: renamable $vpr = MVE_VCMPs32r renamable $q1, $zr, 12, 2, internal killed renamable $vpr…
160 renamable $vpr = MVE_VCMPs32r killed renamable $q0, $zr, 12, 1, killed renamable $vpr, $noreg
162 renamable $vpr = MVE_VCMPs32r renamable $q1, $zr, 12, 1, killed renamable $vpr, $noreg
169 renamable $vpr = MVE_VCMPs32r killed renamable $q0, $zr, 12, 1, killed renamable $vpr, $noreg
180 renamable $vpr = MVE_VCMPs32r renamable $q1, $zr, 12, 1, killed renamable $vpr, $noreg
188 renamable $vpr = MVE_VCMPs32r renamable $q1, $zr, 12, 1, killed renamable $vpr, $noreg
[all …]
H A Dmve-masked-store.ll8 ; CHECK-LE-NEXT: vpt.s32 gt, q0, zr
15 ; CHECK-BE-NEXT: vpt.s32 gt, q1, zr
29 ; CHECK-LE-NEXT: vcmp.s32 gt, q0, zr
68 ; CHECK-BE-NEXT: vcmp.s32 gt, q1, zr
113 ; CHECK-LE-NEXT: vpt.s32 gt, q0, zr
123 ; CHECK-BE-NEXT: vpt.s32 gt, q2, zr
142 ; CHECK-LE-NEXT: vpt.s32 gt, q0, zr
152 ; CHECK-BE-NEXT: vpt.s32 gt, q2, zr
169 ; CHECK-LE-NEXT: vpt.s16 gt, q0, zr
176 ; CHECK-BE-NEXT: vpt.s16 gt, q1, zr
[all …]
H A Dmve-pred-bitcast.ll22 ; CHECK-LE-NEXT: vcmp.i32 ne, q2, zr
45 ; CHECK-BE-NEXT: vcmp.i32 ne, q2, zr
82 ; CHECK-LE-NEXT: vcmp.i16 ne, q1, zr
115 ; CHECK-BE-NEXT: vcmp.i16 ne, q1, zr
175 ; CHECK-LE-NEXT: vcmp.i32 ne, q1, zr
195 ; CHECK-BE-NEXT: vcmp.i32 ne, q1, zr
212 ; CHECK-LE-NEXT: vcmp.i32 eq, q0, zr
235 ; CHECK-BE-NEXT: vcmp.i32 eq, q1, zr
263 ; CHECK-LE-NEXT: vcmp.i16 eq, q0, zr
340 ; CHECK-LE-NEXT: vcmp.i8 eq, q0, zr
[all …]
H A Dmve-zext-masked-load.ll8 ; CHECK-NEXT: vpt.s32 lt, q0, zr
23 ; CHECK-NEXT: vpt.s16 lt, q0, zr
39 ; CHECK-NEXT: vpt.s32 lt, q0, zr
58 ; CHECK-NEXT: vpt.s32 lt, q0, zr
H A Dmve-sext-masked-load.ll9 ; CHECK-NEXT: vpt.s32 lt, q0, zr
24 ; CHECK-NEXT: vpt.s16 lt, q0, zr
40 ; CHECK-NEXT: vpt.s32 lt, q0, zr
58 ; CHECK-NEXT: vpt.s32 lt, q0, zr
H A Dmve-vcmpfz.ll32 ; CHECK-MVEFP-NEXT: vcmp.f32 eq, q0, zr
78 ; CHECK-MVEFP-NEXT: vpt.f32 ge, q0, zr
79 ; CHECK-MVEFP-NEXT: vcmpt.f32 le, q0, zr
115 ; CHECK-MVEFP-NEXT: vcmp.f32 gt, q0, zr
151 ; CHECK-MVEFP-NEXT: vcmp.f32 ge, q0, zr
187 ; CHECK-MVEFP-NEXT: vcmp.f32 lt, q0, zr
223 ; CHECK-MVEFP-NEXT: vcmp.f32 le, q0, zr
269 ; CHECK-MVEFP-NEXT: vpt.f32 ge, q0, zr
298 ; CHECK-MVEFP-NEXT: vcmp.f32 ne, q0, zr
478 ; CHECK-MVEFP-NEXT: vpt.f32 ge, q0, zr
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dldst-opt-zr-clobber.mir5 define i1 @no-clobber-zr(i64* %p, i64 %x) { ret i1 0 }
12 # CHECK-LABEL: name: no-clobber-zr
14 name: no-clobber-zr
/llvm-project-15.0.7/llvm/test/CodeGen/Thumb2/LowOverheadLoops/
H A Dout-of-range-cbz.mir183 ; CHECK: renamable $r0 = t2CSINC $zr, $zr, 10, implicit killed $cpsr
214 ; CHECK: renamable $r0 = t2CSINC $zr, $zr, 10, implicit killed $cpsr
281 ; CHECK: renamable $r2 = t2CSINC $zr, $zr, 10, implicit killed $cpsr
320 renamable $r0 = t2CSINC $zr, $zr, 10, implicit killed $cpsr
359 renamable $r0 = t2CSINC $zr, $zr, 10, implicit killed $cpsr
443 renamable $r2 = t2CSINC $zr, $zr, 10, implicit killed $cpsr

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