x5 (reference) in projects: llvm-project-15.0.7

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Searched refs:x5 (Results 1 – 25 of 573) sorted by relevance

12 3 4 5 6 7 8 9 10 >>...23

/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A D	convert-rr-to-ri-instrs-kill-flag.mir	`49 STD killed $x5, $x5, 100 50 ; CHECK: STD killed $x5, $x5, 100 68 STD $x5, $x5, 100 102 STD killed $x5, $x5, 100 103 ; CHECK: STD killed $x5, $x5, 100 137 STD killed $x5, $x5, 100 138 ; CHECK: STD $x5, $x5, 100 156 STD killed $x5, $x5, 100 157 ; CHECK: STD killed $x5, $x5, 100 175 STD killed $x5, $x5, 100 [all …]`
H A D	convert-rr-to-ri-instr-add.mir	`10 liveins: $x3, $f1, $x5 11 $x3 = ADDI8 $x5, 100 13 ; CHECK: STFS killed $f1, 100, $x5 14 STD killed $x3, killed $x5, 100 15 ; CHECK: STD killed $x3, killed $x5, 100 25 liveins: $x3, $f1, $x5 26 $x3 = ADDI8 $x5, 100 29 STW $r3, $x5, 100 30 ; CHECK: STW killed $r3, $x5, 100 32 ; CHECK: STFS killed $f1, 100, $x5 [all …]`
H A D	topdepthreduce-postra.mir	`5 # because of the dependency on x5 10 ; CHECK: renamable $x5 = LD 0, killed renamable $x5 :: (load (s64)) 12 ; CHECK: renamable $x5 = MULLD killed renamable $x5, renamable $x3 13 … ; CHECK: renamable $x3 = MADDLD8 killed renamable $x4, killed renamable $x3, killed renamable $x5 14 renamable $x5 = LD 0, killed renamable $x5 :: (load (s64)) 15 renamable $x5 = MULLD killed renamable $x5, renamable $x3 17 renamable $x3 = MADDLD8 killed renamable $x4, killed renamable $x3, killed renamable $x5`
H A D	machine-backward-cp.mir	`39 renamable $x5 = LI8 42 76 ; CHECK: renamable $x5 = ADDI8 $x4, 1 80 renamable $x5 = ADDI8 $x4, 1 98 ; CHECK: renamable $x5 = ADDI8 $x3, 1 102 renamable $x5 = ADDI8 $x3, 1 115 liveins: $x3, $x5 118 ; CHECK: liveins: $x3, $x5 120 ; CHECK: renamable $x3 = ADDI8 $x5, 1 124 renamable $x3 = ADDI8 $x5, 1 136 liveins: $x5 [all …]`
H A D	expand-isel-liveness.mir	11 - { reg: '$x5', virtual-reg: '' } 15 liveins: $x3, $x4, $x5, $x6 17 renamable $x8 = MULLD renamable $x5, renamable $x4 23 renamable $cr0 = CMPDI renamable $x5, 0 32 dead renamable $x5 = MULHDU_rec killed renamable $x5, renamable $x4, implicit-def $cr0 36 renamable $x5 = ISEL8 $zero8, killed renamable $x7, killed renamable $cr5lt 37 BLR8 implicit $lr8, implicit $rm, implicit killed $x3, implicit killed $x4, implicit killed $x5 42 ; CHECK: renamable $x5 = ORI8 killed renamable $x7, 0 46 ; CHECK: renamable $x5 = ADDI8 $zero8, 0 48 ; CHECK: liveins: $x3, $x4, $x5 [all …]
H A D	macro-fusion.mir	`14 liveins: $x3, $x4, $x5 16 renamable $x3 = ADD8 killed renamable $x4, $x5 27 liveins: $x3, $x4, $x5 29 renamable $x3 = AND8 killed renamable $x4, $x5 40 liveins: $x3, $x4, $x5 42 renamable $x3 = SUBF8 killed renamable $x4, $x5 53 liveins: $x3, $x4, $x5 92 liveins: $x3, $x4, $x5 105 liveins: $x3, $x4, $x5 118 liveins: $x3, $x4, $x5 [all …]`
H A D	remove-self-copies.mir	`51 - { reg: '$x5', virtual-reg: '' } 76 liveins: $x3, $x4, $x5 83 liveins: $cr0, $x3, $x4, $x5 93 $r5 = OR killed $r4, $r4, implicit $x4, implicit-def $x5 94 $r5 = OR $r5, $r5, implicit-def $x5 95 renamable $x3 = EXTSW_32_64 killed renamable $r5, implicit $x5 100 liveins: $x3, $x4, $x5 109 renamable $r5 = RLWINM killed renamable $r3, 1, 0, 30, implicit $x3, implicit-def $x5 112 liveins: $x5 114 renamable $x3 = EXTSW_32_64 killed renamable $r5, implicit $x5 [all …]`
H A D	remove-redundant-li-implicit-reg.mir	`9 liveins: $x3, $x4, $x5 11 STW killed $r3, killed $x5, 100 12 renamable $x5 = LI8 2 13 renamable $x4 = exact SRD killed renamable $x4, killed renamable $r5, implicit $x5 19 ; CHECK: STW killed $r3, killed $x5, 100`
/llvm-project-15.0.7/llvm/test/MC/AArch64/
H A D	atomic-acquire-comment.s	`7 ldaddab w3, wzr, [x5] 9 ldadda w7, wzr, [x5] 16 ldaddalb w3, wzr, [x5] 18 ldaddal w7, wzr, [x5] 25 ldclrab w3, wzr, [x5] 27 ldclra w7, wzr, [x5] 36 ldclral w7, wzr, [x5] 43 ldeorab w3, wzr, [x5] 45 ldeora w7, wzr, [x5] 63 ldseta w7, wzr, [x5] [all …]`
H A D	armv8.1a-atomic.s	`87 ldsminb w2, w3, [x5] 153 casp x1, x2, x4, x5, [x6] 154 casp x0, x1, x3, x4, [x5] 155 casp x0, x2, x4, x5, [x6] 156 casp x0, x1, x2, x4, [x5] 157 casp x0, w1, x2, x3, [x5] 158 casp w0, x1, x2, x3, [x5] 159 casp w0, x1, w2, w3, [x5] 160 casp x0, x1, w2, w3, [x5]`
H A D	basic-a64-diagnostics.s	`9 add x2, x3, x5, sxtb 73 add sp, x5, x7, lsl 620 adc sp, x3, x5 646 adcs sp, x3, x5 672 sbc sp, x3, x5 698 sbcs sp, x3, x5 848 sxtw x3, x5 860 uxth x5, x9 861 uxtw x3, x5 1128 cbz x3, x5 [all …]`
H A D	arm32-elf-relocs.s	`12 add x5, x7, #:dtprel_lo12:sym 28 add x5, x0, #:tlsdesc_lo12:sym 36 add x5, x7, #:dtprel_lo12:sym+1 52 add x5, x0, #:tlsdesc_lo12:sym+70 119 ldrsb x5, [x6, :tprel_lo12:sym] 158 ldrsh x5, [x6, :tprel_lo12:sym] 171 ldr s4, [x5, :lo12:sym] 181 ldr s4, [x5, #:dtprel_lo12_nc:sym] 192 ldr s4, [x5, :tprel_lo12_nc:sym] 262 add x3, x5, :lo12:imm`
H A D	trace-regs.s	`21 mrs x5, trcdevaff1 22 mrs x5, trclsr 28 mrs x5, trcpidr5 29 mrs x5, trcpidr6 68 mrs x5, trccntrldvr3 129 mrs x5, trcsscsr6 137 mrs x5, trcsspcicr6 162 mrs x5, trcacatr6 184 mrs x5, trcdvcmr4 186 mrs x5, trcdvcmr6 [all …]`
H A D	arm64-elf-relocs.s	`18 add x5, x7, #:dtprel_lo12:sym 34 add x5, x0, #:tlsdesc_lo12:sym 42 add x5, x7, #:dtprel_lo12:sym+1 58 add x5, x0, #:tlsdesc_lo12:sym+70 141 ldrsb x5, [x6, :tprel_lo12:sym] 183 ldrsh x5, [x6, :tprel_lo12:sym] 196 ldr s4, [x5, :lo12:sym] 206 ldr s4, [x5, #:dtprel_lo12_nc:sym] 217 ldr s4, [x5, :tprel_lo12_nc:sym] 310 add x3, x5, :lo12:imm`
/llvm-project-15.0.7/llvm/test/MC/RISCV/
H A D	rv64zbp-aliases-valid.s	`20 zext.h x5, x6 24 rev.p x5, x6 28 rev2.n x5, x6 32 rev.n x5, x6 44 rev.b x5, x6 60 rev.h x5, x6 92 rev8 x5, x6 96 rev4 x5, x6 100 rev2 x5, x6 104 rev x5, x6 [all …]`
H A D	rv32zbp-aliases-valid.s	`20 zext.h x5, x6 24 rev.p x5, x6 28 rev2.n x5, x6 32 rev.n x5, x6 44 rev.b x5, x6 60 rev.h x5, x6 68 rev8 x5, x6 72 rev4 x5, x6 76 rev2 x5, x6 80 rev x5, x6 [all …]`
/llvm-project-15.0.7/llvm/test/Bitcode/
H A D	binaryFloatInstructions.3.2.ll	8 define void @fadd(float %x1, double %x2 ,half %x3, fp128 %x4, x86_fp80 %x5, ppc_fp128 %x6){ 22 ; CHECK-NEXT: %res5 = fadd x86_fp80 %x5, %x5 23 %res5 = fadd x86_fp80 %x5, %x5 31 …faddFloatVec(<2 x float> %x1, <3 x float> %x2 ,<4 x float> %x3, <8 x float> %x4, <16 x float> %x5){ 45 ; CHECK-NEXT: %res5 = fadd <16 x float> %x5, %x5 46 %res5 = fadd <16 x float> %x5, %x5 65 ; CHECK-NEXT: %res5 = fadd <16 x double> %x5, %x5 66 %res5 = fadd <16 x double> %x5, %x5 71 …void @faddHalfVec(<2 x half> %x1, <3 x half> %x2 ,<4 x half> %x3, <8 x half> %x4, <16 x half> %x5){ 85 ; CHECK-NEXT: %res5 = fadd <16 x half> %x5, %x5 [all …]
H A D	binaryIntInstructions.3.2.ll	`8 define void @add(i1 %x1, i8 %x2 ,i16 %x3, i32 %x4, i64 %x5){ 22 ; CHECK-NEXT: %res5 = add i64 %x5, %x5 23 %res5 = add i64 %x5, %x5 51 ; CHECK-NEXT: %res5 = add nuw nsw <16 x i8> %x5, %x5 52 %res5 = add nuw nsw <16 x i8> %x5, %x5 71 ; CHECK-NEXT: %res5 = add nuw nsw <16 x i16> %x5, %x5 72 %res5 = add nuw nsw <16 x i16> %x5, %x5 91 ; CHECK-NEXT: %res5 = add nuw nsw <16 x i32> %x5, %x5 92 %res5 = add nuw nsw <16 x i32> %x5, %x5 111 ; CHECK-NEXT: %res5 = add nuw nsw <16 x i64> %x5, %x5 [all …]`
/llvm-project-15.0.7/llvm/test/tools/llvm-objdump/X86/
H A D	disassemble-same-section-addr.test	`32 # TARGET: callq 0x5 <target> 33 # ABSOLUTE: callq 0x5 <other+0x5> 34 # FAIL: callq 0x5{{$}} 51 Address: 0x5 56 Address: 0x5 61 Value: 0x5 67 # RUN: yaml2obj %s --docnum=2 -o %t7 -D SIZE1=0 -D SIZE2=0 -D SYMVAL1=0x5 -D SYMVAL2=0x5 83 # FIRST: callq 0x5 <first> 84 # SECOND: callq 0x5 <second> 101 Address: 0x5 [all …]`
/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/
H A D	machineoutliner.mir	31 ; RV32I-MO: $x5 = PseudoCALLReg {{.}} @OUTLINED_FUNCTION_0 34 ; RV64I-MO: $x5 = PseudoCALLReg {{.}} @OUTLINED_FUNCTION_0 49 ; RV32I-MO: $x5 = PseudoCALLReg {{.}} @OUTLINED_FUNCTION_0 52 ; RV64I-MO: $x5 = PseudoCALLReg {{.}} @OUTLINED_FUNCTION_0 67 ; RV32I-MO: $x5 = PseudoCALLReg {{.}} @OUTLINED_FUNCTION_0 70 ; RV64I-MO: $x5 = PseudoCALLReg {{.}} @OUTLINED_FUNCTION_0 85 ; RV32I-MO-NOT: $x5 = PseudoCALLReg {{.}} @OUTLINED_FUNCTION_0 88 ; RV64I-MO-NOT: $x5 = PseudoCALLReg {{.}} @OUTLINED_FUNCTION_0 103 ; RV32I-MO-NOT: $x5 = PseudoCALLReg {{.*}} @OUTLINED_FUNCTION_0 119 liveins: $x10, $x11, $x5 [all …]
H A D	machine-outliner-cfi.mir	25 …; RV32I-MO-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $… 30 …; RV64I-MO-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $… 52 …; RV32I-MO-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $… 57 …; RV64I-MO-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $… 79 …; RV32I-MO-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $… 84 …; RV64I-MO-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $… 99 # OUTLINED: liveins: $x11, $x10, $x5 106 # OUTLINED-NEXT: $x0 = JALR $x5, 0
H A D	machine-outliner-position.mir	28 …; RV32I-MO-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $… 35 …; RV64I-MO-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $… 56 …; RV32I-MO-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $… 63 …; RV64I-MO-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $… 84 …; RV32I-MO-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $… 91 …; RV64I-MO-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $…
/llvm-project-15.0.7/clang/test/CodeGen/aarch64-sve-intrinsics/
H A D	acle_sve_dupq.c	227 int8_t x4, int8_t x5, int8_t x6, int8_t x7, in test_svdupq_n_s8() argument 264 int16_t x4, int16_t x5, int16_t x6, int16_t x7) in test_svdupq_n_s16() argument 267 return SVE_ACLE_FUNC(svdupq,_n,_s16,)(x0, x1, x2, x3, x4, x5, x6, x7); in test_svdupq_n_s16() 362 uint8_t x4, uint8_t x5, uint8_t x6, uint8_t x7, in test_svdupq_n_u8() argument 399 uint16_t x4, uint16_t x5, uint16_t x6, uint16_t x7) in test_svdupq_n_u16() argument 402 return SVE_ACLE_FUNC(svdupq,_n,_u16,)(x0, x1, x2, x3, x4, x5, x6, x7); in test_svdupq_n_u16() 481 float16_t x4, float16_t x5, float16_t x6, float16_t x7) in test_svdupq_n_f16() argument 484 return SVE_ACLE_FUNC(svdupq,_n,_f16,)(x0, x1, x2, x3, x4, x5, x6, x7); in test_svdupq_n_f16() 615 bool x4, bool x5, bool x6, bool x7, in test_svdupq_n_b8() argument 674 bool x4, bool x5, bool x6, bool x7) in test_svdupq_n_b16() argument [all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A D	loh.mir	77 ; CHECK-NEXT: $x5 = ADRP target-flags(aarch64-page) @g2 84 $x5 = ADRP target-flags(aarch64-page) @g2 85 $s6 = LDRSui $x5, target-flags(aarch64-pageoff) @g2 96 $x5 = ADRP target-flags(aarch64-page, aarch64-got) @g2 131 $x5 = ADRP target-flags(aarch64-page) @g3 159 ; CHECK-NEXT: $x5 = LDRXui $x5, target-flags(aarch64-pageoff) @g1 168 $x5 = ADRP target-flags(aarch64-page) @g1 169 $x5 = LDRXui $x5, target-flags(aarch64-pageoff) @g1 170 STRXui undef $x11, $x5, 32 177 ; $x5 = LDRXui $x9, 0 [all …]
/llvm-project-15.0.7/llvm/test/tools/llvm-mca/AArch64/Exynos/
H A D	divide-multiply.s	`10 msub x3, x4, x5, x6 13 umulh x5, x6, x7 51 # EM3-NEXT: 1 4 1.00 msub x3, x4, x5, x6 53 # EM3-NEXT: 1 4 1.00 umulh x5, x6, x7 58 # EM4-NEXT: 1 4 1.00 msub x3, x4, x5, x6 60 # EM4-NEXT: 1 4 1.00 umulh x5, x6, x7 65 # EM5-NEXT: 1 3 1.00 msub x3, x4, x5, x6 67 # EM5-NEXT: 1 3 1.00 umulh x5, x6, x7`

12 3 4 5 6 7 8 9 10 >>...23

TaskScheduler
dpdk
expo
f-stack
freebsd-12.1
freebsd-13.1
freebsd-14.2
iperf
leveldb-1.20
libedit-20250104-3.1
libev
libevent-2.1.12
libpciaccess
libtiff-4.0.7
lighttpd1.4
linux-6.15
llvm-project-15.0.7
mOS-networking-stack
memcached-1.4.29
memcached-1.6.32
oneTBB
pciutils
potrace-1.14
redis-3.2.3
rocksdb-6.9
rust-libc-0.2.174
sqlite-3.40.0
tonic
vim-8.2.3635
wasmtime-44.0.1
webrtc
xiu
xnu-11215