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/llvm-project-15.0.7/clang/test/SemaCXX/
H A Denum-bitfield.cpp34 WithUnderlying wu : 3; member
35 } wu = { wu_value }; variable
38 int check_enum_bitfield_promotes_correctly = want_unsigned(wu.wu);
/llvm-project-15.0.7/llvm/test/CodeGen/LoongArch/ir-instruction/
H A Dmul.ll71 ; LA32-NEXT: mulh.wu $a4, $a0, $a2
109 ; LA32-NEXT: mulh.wu $a3, $a0, $a2
145 ; LA32-NEXT: mulh.wu $a0, $a0, $a1
164 ; LA32-NEXT: mulh.wu $a4, $a0, $a2
168 ; LA32-NEXT: mulh.wu $a6, $a1, $a2
173 ; LA32-NEXT: mulh.wu $a6, $a0, $a3
177 ; LA32-NEXT: mulh.wu $a6, $a1, $a3
185 ; LA32-NEXT: mulh.wu $a2, $a2, $a6
191 ; LA32-NEXT: mulh.wu $a6, $a3, $a0
220 ; LA32-NEXT: mulh.wu $a4, $a0, $a2
[all …]
/llvm-project-15.0.7/llvm/test/MC/LoongArch/Basic/Integer/
H A Darith.s112 # CHECK-ASM-AND-OBJ: mulh.wu $a6, $t5, $s1
114 mulh.wu $a6, $t5, $s1
124 # CHECK-ASM-AND-OBJ: div.wu $t7, $s0, $zero
126 div.wu $t7, $s0, $zero
128 # CHECK-ASM-AND-OBJ: mod.wu $s4, $a5, $t5
130 mod.wu $s4, $a5, $t5
155 # CHECK64-ASM-AND-OBJ: alsl.wu $t7, $a4, $s2, 1
157 alsl.wu $t7, $a4, $s2, 1
191 # CHECK64-ASM-AND-OBJ: mulw.d.wu $t5, $fp, $s7
193 mulw.d.wu $t5, $fp, $s7
H A Datomic.s88 # CHECK64-ASM-AND-OBJ: ammax.wu $a5, $a7, $fp
90 ammax.wu $a5, $a7, $fp
96 # CHECK64-ASM-AND-OBJ: ammin.wu $a4, $t6, $s7
98 ammin.wu $a4, $t6, $s7
160 # CHECK64-ASM-AND-OBJ: ammax_db.wu $a5, $a7, $fp
162 ammax_db.wu $a5, $a7, $fp
168 # CHECK64-ASM-AND-OBJ: ammin_db.wu $a4, $t6, $s7
170 ammin_db.wu $a4, $t6, $s7
H A Dmemory.s59 # CHECK64-ASM-AND-OBJ: ld.wu $t2, $t7, 31
61 ld.wu $t2, $t7, 31
95 # CHECK64-ASM-AND-OBJ: ldx.wu $a4, $s1, $s5
97 ldx.wu $a4, $s1, $s5
/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/
H A Dhalf-convert-strict.ll271 ; RV32IZFH-NEXT: fcvt.h.wu fa0, a0
278 ; RV64IZFH-NEXT: fcvt.h.wu fa0, a0
285 ; RV32IDZFH-NEXT: fcvt.h.wu fa0, a0
292 ; RV64IDZFH-NEXT: fcvt.h.wu fa0, a0
302 ; CHECKIZFH-NEXT: fcvt.h.wu fa0, a0
307 ; RV32IDZFH-NEXT: fcvt.h.wu fa0, a0
312 ; RV64IDZFH-NEXT: fcvt.h.wu fa0, a0
385 ; RV32IZFH-NEXT: fcvt.h.wu fa0, a0
391 ; RV64IZFH-NEXT: fcvt.h.wu fa0, a0
624 ; RV32IZFH-NEXT: fcvt.h.wu ft0, a0
[all …]
H A Drv64d-double-convert.ll42 ; RV64ID-NEXT: fcvt.wu.d a0, fa0, rtz
51 ; RV64ID-NEXT: fcvt.wu.d a0, fa0, rtz
69 ; RV64ID-NEXT: fcvt.d.wu fa0, a0
78 ; RV64ID-NEXT: fcvt.d.wu fa0, a0
87 ; RV64ID-NEXT: fcvt.d.wu fa0, a0
H A Drv64f-float-convert-strict.ll43 ; RV64IF-NEXT: fcvt.wu.s a0, fa0, rtz
53 ; RV64IF-NEXT: fcvt.wu.s a0, fa0, rtz
71 ; RV64IF-NEXT: fcvt.s.wu fa0, a0
81 ; RV64IF-NEXT: fcvt.s.wu fa0, a0
90 ; RV64IF-NEXT: fcvt.s.wu fa0, a0
H A Drv64zfh-half-convert.ll42 ; RV64IZFH-NEXT: fcvt.wu.h a0, fa0, rtz
51 ; RV64IZFH-NEXT: fcvt.wu.h a0, fa0, rtz
119 ; RV64IZFH-NEXT: fcvt.h.wu fa0, a0
128 ; RV64IZFH-NEXT: fcvt.h.wu fa0, a0
137 ; RV64IZFH-NEXT: fcvt.h.wu fa0, a0
H A Drv64zfh-half-convert-strict.ll44 ; RV64IZFH-NEXT: fcvt.wu.h a0, fa0, rtz
54 ; RV64IZFH-NEXT: fcvt.wu.h a0, fa0, rtz
72 ; RV64IZFH-NEXT: fcvt.h.wu fa0, a0
82 ; RV64IZFH-NEXT: fcvt.h.wu fa0, a0
91 ; RV64IZFH-NEXT: fcvt.h.wu fa0, a0
H A Drv64f-float-convert.ll42 ; RV64IF-NEXT: fcvt.wu.s a0, fa0, rtz
51 ; RV64IF-NEXT: fcvt.wu.s a0, fa0, rtz
119 ; RV64IF-NEXT: fcvt.s.wu fa0, a0
128 ; RV64IF-NEXT: fcvt.s.wu fa0, a0
137 ; RV64IF-NEXT: fcvt.s.wu fa0, a0
H A Drv64d-double-convert-strict.ll43 ; RV64ID-NEXT: fcvt.wu.d a0, fa0, rtz
53 ; RV64ID-NEXT: fcvt.wu.d a0, fa0, rtz
71 ; RV64ID-NEXT: fcvt.d.wu fa0, a0
81 ; RV64ID-NEXT: fcvt.d.wu fa0, a0
90 ; RV64ID-NEXT: fcvt.d.wu fa0, a0
H A Dfloat-round-conv.ll77 ; RV32IF-NEXT: fcvt.wu.s a0, fa0, rdn
92 ; RV32IF-NEXT: fcvt.wu.s a0, fa0, rdn
107 ; RV32IF-NEXT: fcvt.wu.s a0, fa0, rdn
112 ; RV64IF-NEXT: fcvt.wu.s a0, fa0, rdn
211 ; RV32IF-NEXT: fcvt.wu.s a0, fa0, rup
226 ; RV32IF-NEXT: fcvt.wu.s a0, fa0, rup
241 ; RV32IF-NEXT: fcvt.wu.s a0, fa0, rup
246 ; RV64IF-NEXT: fcvt.wu.s a0, fa0, rup
345 ; RV32IF-NEXT: fcvt.wu.s a0, fa0, rtz
360 ; RV32IF-NEXT: fcvt.wu.s a0, fa0, rtz
[all …]
H A Ddouble-round-conv.ll72 ; RV32IFD-NEXT: fcvt.wu.d a0, fa0, rdn
87 ; RV32IFD-NEXT: fcvt.wu.d a0, fa0, rdn
102 ; CHECKIFD-NEXT: fcvt.wu.d a0, fa0, rdn
196 ; RV32IFD-NEXT: fcvt.wu.d a0, fa0, rup
211 ; RV32IFD-NEXT: fcvt.wu.d a0, fa0, rup
226 ; CHECKIFD-NEXT: fcvt.wu.d a0, fa0, rup
320 ; RV32IFD-NEXT: fcvt.wu.d a0, fa0, rtz
335 ; RV32IFD-NEXT: fcvt.wu.d a0, fa0, rtz
444 ; RV32IFD-NEXT: fcvt.wu.d a0, fa0, rmm
459 ; RV32IFD-NEXT: fcvt.wu.d a0, fa0, rmm
[all …]
/llvm-project-15.0.7/llvm/test/MC/RISCV/
H A Dpriv-rv64-valid.s10 # CHECK-INST: hlv.wu a0, (a1)
13 hlv.wu a0, (a1)
15 # CHECK-INST: hlv.wu a0, (a1)
18 hlv.wu a0, 0(a1)
H A Dpriv-rv64-invalid.s3 hlv.wu a0, 0x10 # CHECK: :[[@LINE]]:17: error: expected '(' after optional integer offset
5 hlv.wu a0, a1 # CHECK: :[[@LINE]]:12: error: expected '(' or optional integer offset
7 hlv.wu a0, 1(a1) # CHECK: :[[@LINE]]:12: error: optional integer offset must be 0
H A Drvzfinx-aliases-valid.s74 # CHECK-INST: fcvt.wu.s a1, s6, dyn
75 # CHECK-ALIAS: fcvt.wu.s a1, s6
76 fcvt.wu.s a1, s6
80 # CHECK-INST: fcvt.s.wu s0, a5, dyn
81 # CHECK-ALIAS: fcvt.s.wu s0, a5
82 fcvt.s.wu s0, a5
H A Drvzhinx-aliases-valid.s74 # CHECK-INST: fcvt.wu.h a1, s6, dyn
75 # CHECK-ALIAS: fcvt.wu.h a1, s6
76 fcvt.wu.h a1, s6
80 # CHECK-INST: fcvt.h.wu s0, a5, dyn
81 # CHECK-ALIAS: fcvt.h.wu s0, a5
82 fcvt.h.wu s0, a5
H A Drv32zfinx-valid.s58 # CHECK-ASM-AND-OBJ: fcvt.wu.s a1, s6, dyn
60 fcvt.wu.s a1, s6, dyn
76 # CHECK-ASM-AND-OBJ: fcvt.s.wu s0, a5, dyn
78 fcvt.s.wu s0, a5, dyn
120 # CHECK-ASM-AND-OBJ: fcvt.wu.s a1, s6, rdn
122 fcvt.wu.s a1, s6, rdn
126 # CHECK-ASM-AND-OBJ: fcvt.s.wu s0, a5, rne
128 fcvt.s.wu s0, a5, rne
H A Drv32zhinx-valid.s58 # CHECK-ASM-AND-OBJ: fcvt.wu.h a1, s6, dyn
60 fcvt.wu.h x11, x22, dyn
76 # CHECK-ASM-AND-OBJ: fcvt.h.wu s0, a5, dyn
78 fcvt.h.wu s0, x15, dyn
120 # CHECK-ASM-AND-OBJ: fcvt.wu.h a1, s6, rdn
122 fcvt.wu.h x11, x22, rdn
126 # CHECK-ASM-AND-OBJ: fcvt.h.wu s0, a5, rne
128 fcvt.h.wu s0, a5, rne
H A Drvzfh-aliases-valid.s91 # CHECK-INST: fcvt.wu.h a1, fs6, dyn
92 # CHECK-ALIAS: fcvt.wu.h a1, fs6{{[[:space:]]}}
93 fcvt.wu.h a1, fs6
97 # CHECK-INST: fcvt.h.wu ft0, a5, dyn
98 # CHECK-ALIAS: fcvt.h.wu ft0, a5{{[[:space:]]}}
99 fcvt.h.wu ft0, a5
H A Drv32f-valid.s90 # CHECK-ASM-AND-OBJ: fcvt.wu.s a1, fs6, dyn
92 fcvt.wu.s a1, fs6, dyn
111 # CHECK-ASM-AND-OBJ: fcvt.s.wu ft0, a5, dyn
113 fcvt.s.wu ft0, a5, dyn
158 # CHECK-ASM-AND-OBJ: fcvt.wu.s a1, fs6, rdn
160 fcvt.wu.s a1, fs6, rdn
164 # CHECK-ASM-AND-OBJ: fcvt.s.wu ft0, a5, rne
166 fcvt.s.wu ft0, a5, rne
H A Drv32zfh-valid.s90 # CHECK-ASM-AND-OBJ: fcvt.wu.h a1, fs6, dyn
92 fcvt.wu.h a1, fs6, dyn
111 # CHECK-ASM-AND-OBJ: fcvt.h.wu ft0, a5, dyn
113 fcvt.h.wu ft0, a5, dyn
158 # CHECK-ASM-AND-OBJ: fcvt.wu.h a1, fs6, rdn
160 fcvt.wu.h a1, fs6, rdn
164 # CHECK-ASM-AND-OBJ: fcvt.h.wu ft0, a5, rne
166 fcvt.h.wu ft0, a5, rne
H A Drvf-aliases-valid.s154 # CHECK-INST: fcvt.wu.s a1, fs6, dyn
155 # CHECK-ALIAS: fcvt.wu.s a1, fs6{{[[:space:]]}}
156 fcvt.wu.s a1, fs6
160 # CHECK-INST: fcvt.s.wu ft0, a5, dyn
161 # CHECK-ALIAS: fcvt.s.wu ft0, a5{{[[:space:]]}}
162 fcvt.s.wu ft0, a5
/llvm-project-15.0.7/flang/test/Semantics/
H A Dtypeinfo01.f90134 procedure :: rf, ru, wf, wu method
138 generic :: write(unformatted) => wu
163 subroutine wu(x,u,iostat,iomsg) subroutine
187 procedure :: wu
212 subroutine wu(x,u,iostat,iomsg) subroutine

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