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/llvm-project-15.0.7/libc/test/src/string/memory_utils/
H A Dmemory_access_test.cpp46 writes.Reset(); in Reset()
50 BufferAccess __attribute__((aligned(64))) writes; member
60 Buffer1.writes.Touch(Buffer1.Offset(ptr), size); in ObserveWrite()
116 ASSERT_STREQ(src().writes, untouched); in checkOperations()
119 ASSERT_STREQ(dst().writes, expected); in checkOperations()
122 ASSERT_STREQ(lhs().writes, untouched); in checkOperations()
123 ASSERT_STREQ(rhs().writes, untouched); in checkOperations()
129 ASSERT_STREQ(lhs().writes, untouched); in checkOperations()
130 ASSERT_STREQ(rhs().writes, untouched); in checkOperations()
136 ASSERT_STREQ(src().writes, untouched); in checkOperations()
[all …]
/llvm-project-15.0.7/llvm/test/MC/Mips/
H A Dmips-reginfo-fp32.s25 # abs.s - Reads and writes from/to $f0.
27 # round.w.d - Reads $f4 and $f5 and writes to $f2.
29 # ceil.w.s - Reads $f8 and writes to $f10.
31 # cvt.s.d - Reads from $f12 and $f13 and writes to $f14
33 # abs.d - Reads from $f30 and $f31 and writes to $f30 and $f31.
H A Dmips-reginfo-fp64.s47 # abs.s - Reads and writes from/to $f0.
49 # round.w.d - Reads $f4 and writes to $f2.
51 # ceil.w.s - Reads $f8 and writes to $f10.
53 # cvt.s.d - Reads from $f12 and writes to $f14.
55 # abs.d - Reads from $f30 and writes to $f30.
/llvm-project-15.0.7/llvm/bindings/ocaml/bitwriter/
H A Dllvm_bitwriter.mli14 (** [write_bitcode_file m path] writes the bitcode for module [m] to the file at
20 (** [write_bitcode_to_fd ~unbuffered fd m] writes the bitcode for module
33 (** [output_bitcode ~unbuffered c m] writes the bitcode for module [m]
/llvm-project-15.0.7/mlir/python/mlir/dialects/linalg/opdsl/lang/
H A Dconfig.py124 self.writes = list() # type: List[Tuple[TensorUse, TensorExpression]]
136 self.writes.append((write_use, read_use))
138 for write_use, read_use in self.writes:
221 for write_use, _ in self.writes:
230 for _, read_expr in self.writes:
275 for write_use, read_expr in self.writes
/llvm-project-15.0.7/polly/test/Simplify/
H A Dredundant.ll4 ; Remove redundant store (a store that writes the same value already
37 ; CHECK: Redundant writes removed: 1
H A Dredundant_region.ll3 ; Remove redundant store (a store that writes the same value already
45 ; CHECK: Redundant writes removed: 2
H A Dredundant_region_scalar.ll3 ; Remove redundant store (a store that writes the same value already
49 ; CHECK: Redundant writes removed: 3
H A Dnocoalesce_differentvalues.ll38 ; CHECK: Partial writes coalesced: 0
H A Dredundant_scalarwrite.ll45 ; CHECK: Redundant writes removed: 2
/llvm-project-15.0.7/lld/ELF/Arch/
H A DRISCV.cpp501 SmallVector<uint32_t, 0> writes; member
562 sec.relaxAux->writes.push_back(0xa001); // c.j in relaxCall()
567 sec.relaxAux->writes.push_back(0x2001); // c.jal in relaxCall()
571 sec.relaxAux->writes.push_back(0x6f | rd << 7); // jal in relaxCall()
594 sec.relaxAux->writes.push_back(setLO12_I(insn, val)); in relaxTlsLe()
600 sec.relaxAux->writes.push_back(setLO12_S(insn, val)); in relaxTlsLe()
628 aux.writes.clear(); in relax()
776 write16le(p, aux.writes[writesIdx++]); in riscvFinalizeRelax()
780 write32le(p, aux.writes[writesIdx++]); in riscvFinalizeRelax()
786 write32le(p, aux.writes[writesIdx++]); in riscvFinalizeRelax()
/llvm-project-15.0.7/polly/test/DeLICM/
H A Dreduction_overapproximate.ll1 …delicm-compute-known=true -polly-delicm-overapproximate-writes=true -polly-delicm-partial-writes=f…
2 …delicm-compute-known=true -polly-delicm-overapproximate-writes=false -polly-delicm-partial-writes=…
3 …-flatten-schedule -polly-delicm-compute-known=true -polly-delicm-partial-writes=true -polly-print-…
H A Dskip_multiaccess.ll7 ; The the regular store then writes multiple of these subelements, which
70 ; CHECK: skipped possible mapping target because it writes more than one element
H A Dnomap_writewrite.ll19 ; explicit write, defined to occur always before all implicit writes as the
21 ; implicit and explicit writes in Polly.
/llvm-project-15.0.7/llvm/include/llvm/Target/
H A DTargetSchedule.td218 // operand that both reads and writes a reg. In both cases we have a
237 // Variadic, then the list of prior writes are distributed across all
242 list<SchedWrite> Writes = writes;
264 // true for at least one of its writes. This field is only used by
294 // should define one of the writes to be zero micro-ops. If a
297 // or require additional writes. Extra writes can be required either
298 // by defining a WriteSequence, or simply listing extra writes in the
317 class ProcReadAdvance<int cycles, list<SchedWrite> writes = []> {
319 list<SchedWrite> ValidWrites = writes;
337 : ProcReadAdvance<cycles, writes> {
[all …]
/llvm-project-15.0.7/llvm/test/Analysis/Lint/
H A Dnoalias-readonly.ll12 ; argument may depend on writes to the other.
24 ; Lint should complain about us passing %a to both arguments, since writes to
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dpr30290.ll4 ; reads/writes from/to byval storage re-ordered.
7 ; before those writes, illegally.
/llvm-project-15.0.7/clang-tools-extra/docs/clang-tidy/checks/clang-analyzer/
H A Dosx.cocoa.AutoreleaseWrite.rst6 Warn about potentially crashing writes to autoreleasing objects from different autoreleasing pools …
/llvm-project-15.0.7/llvm/test/Analysis/LoopAccessAnalysis/
H A Dnumber-of-memchecks.ll6 ; 3 reads and 3 writes should need 12 memchecks
76 ; 3 reads and 2 writes - two of the reads can be merged,
77 ; and the writes can be merged as well. This gives us a
148 ; 3 reads and 2 writes - the writes can be merged into a single
/llvm-project-15.0.7/llvm/test/tools/llvm-mca/AArch64/Cortex/IPC/
H A DA55-11-fma-mix.s4 # FMADD writes and retires out-of-order
/llvm-project-15.0.7/llvm/test/MC/Hexagon/
H A Dmultiple-pc4.s14 # Multiple writes to the same predicate register are permitted:
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dpostra-machine-sink.mir3 # Don't sink copy that writes sub-register of another copy source register
/llvm-project-15.0.7/llvm/test/tools/llvm-mca/X86/BtVer2/
H A Dclear-super-register-2.s7 # the VDIVPS. That VADDPS also writes to register XMM3, and the upper half of
/llvm-project-15.0.7/llvm/test/tools/llvm-mca/X86/BdVer2/
H A Dclear-super-register-2.s7 # the VDIVPS. That VADDPS also writes to register XMM3, and the upper half of
/llvm-project-15.0.7/lld/test/ELF/
H A Drelocation-b-aarch64.test7 # Check that the R_AARCH64_JUMP26 writes the branch opcode as well as the

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