Home
last modified time | relevance | path

Searched refs:wr (Results 1 – 16 of 16) sorted by relevance

/llvm-project-15.0.7/llvm/test/MC/Sparc/
H A Dsparc-special-registers.s10 ! CHECK: wr %i0, 5, %y ! encoding: [0x81,0x86,0x20,0x05]
11 wr %i0, 5, %y
13 ! CHECK: wr %i0, %i1, %asr15 ! encoding: [0x9f,0x86,0x00,0x19]
14 wr %i0, %i1, %asr15
28 ! CHECK: wr %i0, 5, %psr ! encoding: [0x81,0x8e,0x20,0x05]
29 wr %i0, 5, %psr
31 ! CHECK: wr %i0, 5, %wim ! encoding: [0x81,0x96,0x20,0x05]
32 wr %i0, 5, %wim
35 wr %i0, 5, %tbr
40 ! CHECK: wr %i0, 7, %asr6 ! encoding: [0x8d,0x86,0x20,0x07]
[all …]
H A Dsparc-synthetic-instructions.s124 ! CHECK: wr %g0, %i0, %y ! encoding: [0x81,0x80,0x00,0x18]
147 wr %i0, %y
149 wr 5, %y
151 wr %i0, %asr15
153 wr 5, %asr15
155 wr %i0, %psr
157 wr 5, %psr
159 wr %i0, %wim
161 wr 5, %wim
163 wr %i0, %tbr
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Dfpextend_x86.ll7 %wr = fadd x86_fp80 %wa, %wb
8 %r = fptrunc x86_fp80 %wr to double
18 %wr = fsub x86_fp80 %wa, %wb
19 %r = fptrunc x86_fp80 %wr to double
29 %wr = fmul x86_fp80 %wa, %wb
30 %r = fptrunc x86_fp80 %wr to double
40 %wr = fmul x86_fp80 %wa, %wb
41 %r = fptrunc x86_fp80 %wr to double
51 %wr = fdiv x86_fp80 %wa, %wb
52 %r = fptrunc x86_fp80 %wr to double
/llvm-project-15.0.7/llvm/test/MC/Disassembler/Sparc/
H A Dsparc-special-registers.txt3 # CHECK: wr %g1, -2, %y
12 # CHECK: wr %i0, 5, %y
15 # CHECK: wr %i0, %i1, %asr15
27 # CHECK: wr %i0, 5, %psr
30 # CHECK: wr %i0, 5, %wim
33 # CHECK: wr %i0, 5, %tbr
/llvm-project-15.0.7/libcxx/test/std/language.support/support.coroutines/end.to.end/
H A Dgo.pass.cpp120 auto wr = writer; in sync_pull() local
122 wr(); in sync_pull()
146 auto wr = ch->writer; in await_resume() local
148 wr(); in await_resume()
/llvm-project-15.0.7/libcxx/test/std/experimental/language.support/support.coroutines/end.to.end/
H A Dgo.pass.cpp122 auto wr = writer; in sync_pull() local
124 wr(); in sync_pull()
148 auto wr = ch->writer; in await_resume() local
150 wr(); in await_resume()
/llvm-project-15.0.7/llvm/test/CodeGen/SPARC/
H A Dmultiple-div.ll6 ;; apparently-redundant wr to %y, which is not actually redundant
10 ; CHECK: wr %g0, %g0, %y
12 ; CHECK: wr %g0, %g0, %y
H A Dbasictest.ll41 ; CHECK: wr %g0, %o2, %y
49 ; CHECK: wr %g0, %g0, %y
/llvm-project-15.0.7/llvm/test/DebugInfo/
H A Dsymbolize-filter-markup-mmap.test16 ERR: error: expected mode; found 'wr'
37 {{{mmap:0:10000000:load:0:wr:0}}}
/llvm-project-15.0.7/llvm/lib/Target/Sparc/
H A DSparcInstrAliases.td449 // mov reg_or_imm, specialreg -> wr %g0, reg_or_imm, specialreg
461 // wr reg_or_imm, specialreg -> wr %g0, reg_or_imm, specialreg
464 def : InstAlias<"wr $rs2, $asr", (WRASRrr ASRRegs:$asr, G0, IntRegs:$rs2), 0>;
465 def : InstAlias<"wr $simm13, $asr", (WRASRri ASRRegs:$asr, G0, i32imm:$simm13), 0>;
466 def : InstAlias<"wr $rs2, %psr", (WRPSRrr G0, IntRegs:$rs2), 0>;
467 def : InstAlias<"wr $simm13, %psr", (WRPSRri G0, i32imm:$simm13), 0>;
468 def : InstAlias<"wr $rs2, %wim", (WRWIMrr G0, IntRegs:$rs2), 0>;
469 def : InstAlias<"wr $simm13, %wim", (WRWIMri G0, i32imm:$simm13), 0>;
470 def : InstAlias<"wr $rs2, %tbr", (WRTBRrr G0, IntRegs:$rs2), 0>;
471 def : InstAlias<"wr $simm13, %tbr", (WRTBRri G0, i32imm:$simm13), 0>;
H A DSparcInstrInfo.td1128 "wr $rs1, $rs2, $rd", []>;
1131 "wr $rs1, $simm13, $rd", []>;
1138 "wr $rs1, $rs2, %psr", []>;
1141 "wr $rs1, $simm13, %psr", []>;
1147 "wr $rs1, $rs2, %wim", []>;
1150 "wr $rs1, $simm13, %wim", []>;
1156 "wr $rs1, $rs2, %tbr", []>;
1159 "wr $rs1, $simm13, %tbr", []>;
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMSchedule.td195 list<int> rcl, SchedWriteRes wr> :
196 SchedWriteRes<!listconcat(wr.ProcResources, resl)> {
197 let Latency = !add(wr.Latency, lat);
198 let ResourceCycles = !listconcat(wr.ResourceCycles, rcl);
199 let NumMicroOps = !add(wr.NumMicroOps, uops);
200 SchedWriteRes BaseWr = wr;
/llvm-project-15.0.7/compiler-rt/lib/stats/
H A Dstats.cpp134 } wr; variable
/llvm-project-15.0.7/openmp/runtime/src/
H A Dkmp_atomic.cpp2158 ATOMIC_XCHG_WR(fixed1, wr, kmp_int8, 8, =,
2160 ATOMIC_XCHG_WR(fixed2, wr, kmp_int16, 16, =,
2162 ATOMIC_XCHG_WR(fixed4, wr, kmp_int32, 32, =,
2165 ATOMIC_CMPXCHG_WR(fixed8, wr, kmp_int64, 64, =,
2168 ATOMIC_XCHG_WR(fixed8, wr, kmp_int64, 64, =,
2172 ATOMIC_XCHG_FLOAT_WR(float4, wr, kmp_real32, 32, =,
2175 ATOMIC_CMPXCHG_WR(float8, wr, kmp_real64, 64, =,
2178 ATOMIC_XCHG_FLOAT_WR(float8, wr, kmp_real64, 64, =,
2182 ATOMIC_CRITICAL_WR(float10, wr, long double, =, 10r,
2185 ATOMIC_CRITICAL_WR(float16, wr, QUAD_LEGACY, =, 16r,
[all …]
/llvm-project-15.0.7/llvm/test/MC/RISCV/
H A Drv32i-invalid.s6 fence wr, wr # CHECK: :[[@LINE]]:7: error: operand must be formed of letters selected in-order from…
/llvm-project-15.0.7/compiler-rt/lib/sanitizer_common/
H A Dsanitizer_common_interceptors.inc6134 xdrrec_cb rd, wr;
6143 return wrap->wr(wrap->handle, buf, count);
6156 int (*wr)(char*, char*, int)) {
6159 handle, rd, wr);
6170 wrap_data->wr = wr;
6171 if (wr)
6172 wr = xdrrec_wr_wrap;
6177 REAL(xdrrec_create)(xdr, sndsize, rcvsize, handle, rd, wr);