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/llvm-project-15.0.7/llvm/test/CodeGen/Hexagon/intrinsics/
H A Dv65-gather.ll4 ; CHECK: vtmp.w = vgather(r1,m{{[0-9]+}},v{{[0-9]+}}.w).w
5 ; CHECK: vmem(r{{[0-9]+}}+#0) = vtmp.new
7 ; CHECK: vtmp.h = vgather(r1,m{{[0-9]+}},v{{[0-9]+}}.h).h
8 ; CHECK: vmem(r{{[0-9]+}}+#0) = vtmp.new
10 ; CHECK: vtmp.h = vgather(r1,m{{[0-9]+}},v{{[0-9]+}}:{{[0-9]+}}.w).h
11 ; CHECK: vmem(r{{[0-9]+}}+#0) = vtmp.new
13 ; CHECK: if (q{{[0-3]+}}) vtmp.w = vgather(r1,m{{[0-9]+}},v{{[0-9]+}}.w).w
14 ; CHECK: vmem(r{{[0-9]+}}+#0) = vtmp.new
16 ; CHECK: if (q{{[0-3]+}}) vtmp.h = vgather(r1,m{{[0-9]+}},v{{[0-9]+}}.h).h
17 ; CHECK: vmem(r{{[0-9]+}}+#0) = vtmp.new
[all …]
H A Dv65-gather-double.ll4 ; CHECK: vtmp.w = vgather(r1,m{{[0-9]+}},v{{[0-9]+}}.w).w
5 ; CHECK: vmem(r{{[0-9]+}}+#0) = vtmp.new
7 ; CHECK: vtmp.h = vgather(r1,m{{[0-9]+}},v{{[0-9]+}}.h).h
8 ; CHECK: vmem(r{{[0-9]+}}+#0) = vtmp.new
10 ; CHECK: vtmp.h = vgather(r1,m{{[0-9]+}},v{{[0-9]+}}:{{[0-9]+}}.w).h
11 ; CHECK: vmem(r{{[0-9]+}}+#0) = vtmp.new
13 ; CHECK: if (q{{[0-3]+}}) vtmp.w = vgather(r1,m{{[0-9]+}},v{{[0-9]+}}.w).w
14 ; CHECK: vmem(r{{[0-9]+}}+#0) = vtmp.new
16 ; CHECK: if (q{{[0-3]+}}) vtmp.h = vgather(r1,m{{[0-9]+}},v{{[0-9]+}}.h).h
17 ; CHECK: vmem(r{{[0-9]+}}+#0) = vtmp.new
[all …]
H A Dv65-scatter-gather.ll5 ; CHECK: vtmp.h = vgather(r{{[0-9]+}},m{{[0-9]+}},v{{[0-9]+}}.h).h
6 ; CHECK-NEXT: vmem(r{{[0-9]+}}+#0) = vtmp.new
/llvm-project-15.0.7/llvm/test/MC/Hexagon/
H A Dv65_all.s16 if (Q0) vtmp.w=vgather(R0,M0,V0.w).w
17 # CHECK: 2f00c400 { if (q0) vtmp.w = vgather(r0,m0,v0.w).w }
36 if (Q0) vtmp.h=vgather(R0,M0,V1:0.w).h
37 # CHECK: 2f00c600 { if (q0) vtmp.h = vgather(r0,m0,v1:0.w).h }
46 vtmp.h=vgather(R0,M0,V0.h).h
47 # CHECK: 2f00c100 { vtmp.h = vgather(r0,m0,v0.h).h }
81 vtmp.w=vgather(R0,M0,V0.w).w
82 # CHECK: 2f00c000 { vtmp.w = vgather(r0,m0,v0.w).w }
96 if (Q0) vtmp.h=vgather(R0,M0,V0.h).h
111 vtmp.h=vgather(R0,M0,V1:0.w).h
[all …]
H A Dvgather-new.s9 if (q0) vtmp.h = vgather(r5,m0,v31.h).h
10 vmem(r1+#0) = vtmp.new
/llvm-project-15.0.7/llvm/test/CodeGen/Hexagon/
H A Dvgather-opt-addr.ll11 ; CHECK-NO-AMODE: vmem([[REG1]]+#0) = vtmp.new
12 ; CHECK-NO-AMODE: vmem([[REG2]]+#0) = vtmp.new
13 ; CHECK-NO-AMODE: vmem([[REG3]]+#0) = vtmp.new
14 ; CHECK-NO-AMODE: vmem([[REG4]]+#0) = vtmp.new
15 ; CHECK-NO-AMODE: vmem([[REG5]]+#0) = vtmp.new
21 ; CHECK-AMODE: vmem([[REG1]]+#0) = vtmp.new
22 ; CHECK-AMODE: vmem([[REG1]]+#1) = vtmp.new
23 ; CHECK-AMODE: vmem([[REG1]]+#2) = vtmp.new
24 ; CHECK-AMODE: vmem([[REG1]]+#3) = vtmp.new
25 ; CHECK-AMODE: vmem([[REG1]]+#4) = vtmp.new
[all …]
H A Dvgather-packetize.mir7 # CHECK-NEXT: vtmp.h = vgather
8 # CHECK-NEXT: vmem(r0+#0) = vtmp.new
24 V6_vgathermhw_pseudo killed $r0, 0, killed $r2, killed $m0, killed $w0, implicit-def $vtmp
H A Dno-packets-gather.ll18 ; CHECK-NEXT: vtmp.w = vgather(r1,m0,v0.w).w
19 ; CHECK-NEXT: vmem(r0+#0) = vtmp.new
/llvm-project-15.0.7/libc/AOR_v20.02/networking/arm/
H A Dchksum_simd.c43 uint32x2_t vtmp = vreinterpret_u32_u64(vword64); in __chksum_arm_simd() local
45 vsum = vpaddl_u32(vtmp); in __chksum_arm_simd()
96 uint32x2_t vtmp = vmovn_u64(vsum0); in __chksum_arm_simd() local
98 vsum = vpadal_u32(vsum, vtmp); in __chksum_arm_simd()
104 uint32x2_t vtmp = vld1_u32(ptr32); in __chksum_arm_simd() local
106 vsum = vpadal_u32(vsum, vtmp); in __chksum_arm_simd()
/llvm-project-15.0.7/llvm/test/MC/Hexagon/PacketRules/
H A Dnewvalue_producers_pass.s23 { vtmp.h=vgather(r0,m0,v0.h).h
24 vmem(r0)=vtmp.new }
25 # CHECK: { vtmp.h = vgather(r0,m0,v0.h).h
26 # CHECK: vmem(r0+#0) = vtmp.new }
/llvm-project-15.0.7/libc/AOR_v20.02/networking/aarch64/
H A Dchksum_simd.c121 uint32x4_t vtmp = vld1q_u32(ptr32); in __chksum_aarch64_simd() local
122 vsum0 = vpadalq_u32(vsum0, vtmp); in __chksum_aarch64_simd()
131 uint32x2_t vtmp = vld1_u32(ptr32); in __chksum_aarch64_simd() local
132 vsum0 = vaddw_u32(vsum0, vtmp); in __chksum_aarch64_simd()
/llvm-project-15.0.7/polly/lib/External/isl/imath/
H A Dimath.c428 mpz_t vtmp; in mp_int_init_value() local
436 mpz_t vtmp; in mp_int_init_uvalue() local
444 mpz_t vtmp; in mp_int_set_value() local
452 mpz_t vtmp; in mp_int_set_uvalue() local
595 mpz_t vtmp; in mp_int_add_value() local
657 mpz_t vtmp; in mp_int_sub_value() local
716 mpz_t vtmp; in mp_int_mul_value() local
873 mpz_t vtmp; in mp_int_div_value() local
1067 mpz_t vtmp; in mp_int_exptmod_evalue() local
1076 mpz_t vtmp; in mp_int_exptmod_bvalue() local
[all …]
/llvm-project-15.0.7/llvm/test/MC/Hexagon/extensions/
H A Dv67_hvx.s1434 vtmp.h=vgather(r0,m0,v0.h).h
1435 # CHECK-NEXT: 2f00c100 { vtmp.h = vgather(r0,m0,v0.h).h }
1439 if (q0) vtmp.h=vgather(r0,m0,v0.h).h
1440 # CHECK-NEXT: 2f00c500 { if (q0) vtmp.h = vgather(r0,m0,v0.h).h }
1444 vtmp.h=vgather(r0,m0,v1:0.w).h
1445 # CHECK-NEXT: 2f00c200 { vtmp.h = vgather(r0,m0,v1:0.w).h }
1449 if (q0) vtmp.h=vgather(r0,m0,v1:0.w).h
1454 vtmp.w=vgather(r0,m0,v0.w).w
1455 # CHECK-NEXT: 2f00c000 { vtmp.w = vgather(r0,m0,v0.w).w }
1459 if (q0) vtmp.w=vgather(r0,m0,v0.w).w
[all …]
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonRegisterInfo.td228 def VTMP : Ri<0, "vtmp">, DwarfRegNum<[131]>;
H A DHexagonDepInstrInfo.td33378 "vtmp.h = vgather($Rt32,$Mu2,$Vv32.h).h",
33394 "if ($Qs4) vtmp.h = vgather($Rt32,$Mu2,$Vv32.h).h",
33410 "vtmp.h = vgather($Rt32,$Mu2,$Vvv32.w).h",
33426 "if ($Qs4) vtmp.h = vgather($Rt32,$Mu2,$Vvv32.w).h",
33442 "vtmp.w = vgather($Rt32,$Mu2,$Vv32.w).w",
33458 "if ($Qs4) vtmp.w = vgather($Rt32,$Mu2,$Vv32.w).w",