Home
last modified time | relevance | path

Searched refs:vsx (Results 1 – 25 of 190) sorted by relevance

12345678

/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A Dbuiltins-ppc-elf2-abi.ll143 %1 = call <4 x float> @llvm.ppc.vsx.xvresp(<4 x float> %0)
250 declare <4 x float> @llvm.ppc.vsx.xvresp(<4 x float>)
253 declare <2 x double> @llvm.ppc.vsx.xvredp(<2 x double>)
284 declare <4 x float> @llvm.ppc.vsx.xvcvdpsp(<2 x double>) #1
285 declare <4 x i32> @llvm.ppc.vsx.xvcvdpsxws(<2 x double>) #1
287 declare <2 x double> @llvm.ppc.vsx.xvcvsxwdp(<4 x i32>) #1
288 declare <2 x double> @llvm.ppc.vsx.xvcvuxwdp(<4 x i32>) #1
290 declare <4 x float> @llvm.ppc.vsx.xvcvsxdsp(<2 x i64>) #1
291 declare <4 x float> @llvm.ppc.vsx.xvcvuxdsp(<2 x i64>) #1
292 declare <2 x i64> @llvm.ppc.vsx.xvcvspsxds(<4 x float>) #1
[all …]
H A Dvsx-minmax.ll23 %2 = tail call <4 x float> @llvm.ppc.vsx.xvmaxsp(<4 x float> %0, <4 x float> %1)
32 %7 = tail call <4 x float> @llvm.ppc.vsx.xvmaxsp(<4 x float> %5, <4 x float> %6)
50 %17 = tail call double @llvm.ppc.vsx.xsmaxdp(double %16, double %16)
53 %18 = tail call double @llvm.ppc.vsx.xsmindp(double %16, double %16)
60 declare double @llvm.ppc.vsx.xsmaxdp(double, double)
63 declare double @llvm.ppc.vsx.xsmindp(double, double)
66 declare <4 x float> @llvm.ppc.vsx.xvminsp(<4 x float>, <4 x float>)
69 declare <2 x double> @llvm.ppc.vsx.xvmindp(<2 x double>, <2 x double>)
72 declare <4 x float> @llvm.ppc.vsx.xvmaxsp(<4 x float>, <4 x float>)
75 declare <2 x double> @llvm.ppc.vsx.xvmaxdp(<2 x double>, <2 x double>)
[all …]
H A Di64_fp.ll4 ; RUN: llc -verify-machineinstrs < %s -mattr=-vsx -mtriple=ppc32-- -mattr=+64bit | \
6 ; RUN: llc -verify-machineinstrs < %s -mattr=-vsx -mtriple=ppc32-- -mattr=+64bit | \
8 ; RUN: llc -verify-machineinstrs < %s -mattr=-vsx -mtriple=ppc32-- -mcpu=g5 | \
10 ; RUN: llc -verify-machineinstrs < %s -mattr=-vsx -mtriple=ppc32-- -mcpu=g5 | \
12 ; RUN: llc -verify-machineinstrs < %s -mattr=-vsx -mtriple=ppc32-- -mattr=-64bit | \
14 ; RUN: llc -verify-machineinstrs < %s -mattr=-vsx -mtriple=ppc32-- -mattr=-64bit | \
16 ; RUN: llc -verify-machineinstrs < %s -mattr=-vsx -mtriple=ppc32-- -mcpu=g4 | \
18 ; RUN: llc -verify-machineinstrs < %s -mattr=-vsx -mtriple=ppc32-- -mcpu=g4 | \
H A Dvsx-ldst-builtin-le.ll1 ; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mattr=+vsx -O2 \
34 %0 = call <4 x i32> @llvm.ppc.vsx.lxvw4x(i8* bitcast (<4 x i32>* @vsi to i8*))
40 %1 = call <4 x i32> @llvm.ppc.vsx.lxvw4x(i8* bitcast (<4 x i32>* @vui to i8*))
46 %2 = call <4 x i32> @llvm.ppc.vsx.lxvw4x(i8* bitcast (<4 x float>* @vf to i8*))
53 %4 = call <2 x double> @llvm.ppc.vsx.lxvd2x(i8* bitcast (<2 x i64>* @vsll to i8*))
60 %6 = call <2 x double> @llvm.ppc.vsx.lxvd2x(i8* bitcast (<2 x i64>* @vull to i8*))
67 %8 = call <2 x double> @llvm.ppc.vsx.lxvd2x(i8* bitcast (<2 x double>* @vd to i8*))
113 declare void @llvm.ppc.vsx.stxvd2x(<2 x double>, i8*)
114 declare void @llvm.ppc.vsx.stxvw4x(<4 x i32>, i8*)
115 declare <2 x double> @llvm.ppc.vsx.lxvd2x(i8*)
[all …]
H A Dvsx_builtins.ll10 ; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mattr=+vsx \
22 ; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mattr=+vsx \
42 %0 = tail call <4 x i32> @llvm.ppc.vsx.lxvw4x.be(i8* %a)
46 declare <4 x i32> @llvm.ppc.vsx.lxvw4x.be(i8*)
59 declare <2 x double> @llvm.ppc.vsx.lxvd2x.be(i8*)
72 declare void @llvm.ppc.vsx.stxvw4x.be(<4 x i32>, i8*)
85 declare void @llvm.ppc.vsx.stxvd2x.be(<2 x double>, i8*)
124 declare i32 @llvm.ppc.vsx.xvtsqrtdp(<2 x double>)
137 declare i32 @llvm.ppc.vsx.xvtsqrtsp(<4 x float>)
195 declare <2 x double> @llvm.ppc.vsx.lxvd2x(i8*)
[all …]
H A Dp10-vsx-pcv.ll8 declare <16 x i8> @llvm.ppc.vsx.xxgenpcvbm(<16 x i8>, i32)
9 declare <8 x i16> @llvm.ppc.vsx.xxgenpcvhm(<8 x i16>, i32)
10 declare <4 x i32> @llvm.ppc.vsx.xxgenpcvwm(<4 x i32>, i32)
11 declare <2 x i64> @llvm.ppc.vsx.xxgenpcvdm(<2 x i64>, i32)
19 %gen = tail call <16 x i8> @llvm.ppc.vsx.xxgenpcvbm(<16 x i8> %a, i32 1)
29 %gen = tail call <8 x i16> @llvm.ppc.vsx.xxgenpcvhm(<8 x i16> %a, i32 1)
39 %gen = tail call <4 x i32> @llvm.ppc.vsx.xxgenpcvwm(<4 x i32> %a, i32 1)
49 %gen = tail call <2 x i64> @llvm.ppc.vsx.xxgenpcvdm(<2 x i64> %a, i32 1)
H A Dppc-passname.ll25 ; Test pass name: ppc-vsx-copy.
27 ; STOP-BEFORE-VSX-COPY-NOT: -ppc-vsx-copy
28 ; STOP-BEFORE-VSX-COPY-NOT: "ppc-vsx-copy" pass is not registered.
32 ; STOP-AFTER-VSX-COPY: -ppc-vsx-copy
33 ; STOP-AFTER-VSX-COPY-NOT: "ppc-vsx-copy" pass is not registered.
49 ; Test pass name: ppc-vsx-fma-mutate.
51 ; STOP-BEFORE-VSX-FMA-MUTATE-NOT: -ppc-vsx-fma-mutate
56 ; STOP-AFTER-VSX-FMA-MUTATE: -ppc-vsx-fma-mutate
61 ; Test pass name: ppc-vsx-swaps.
63 ; STOP-BEFORE-VSX-SWAPS-NOT: -ppc-vsx-swaps
[all …]
H A Dvsx-p9.ll249 declare <4 x float> @llvm.ppc.vsx.xvcvsphp(<4 x float>)
272 declare <4 x i32> @llvm.ppc.vsx.xvxexpsp(<4 x float>)
284 declare <2 x i64>@llvm.ppc.vsx.xvxexpdp(<2 x double>)
296 declare <4 x i32> @llvm.ppc.vsx.xvxsigsp(<4 x float>)
308 declare <2 x i64> @llvm.ppc.vsx.xvxsigdp(<2 x double>)
343 declare <4 x float>@llvm.ppc.vsx.xvcvhpsp(<8 x i16>)
348 %0 = tail call <4 x i32> @llvm.ppc.vsx.lxvl(i8* %a, i64 %b)
355 declare <4 x i32> @llvm.ppc.vsx.lxvl(i8*, i64)
366 declare void @llvm.ppc.vsx.stxvl(<4 x i32>, i8*, i64)
378 declare <4 x i32> @llvm.ppc.vsx.lxvll(i8*, i64)
[all …]
H A Dvsx-div.ll1 ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=+vsx -O1 -mtriple=powerpc64-unknown-linux-gnu < …
11 %1 = tail call <4 x float> @llvm.ppc.vsx.xvdivsp(<4 x float> %0, <4 x float> %0)
21 %1 = tail call <2 x double> @llvm.ppc.vsx.xvdivdp(<2 x double> %0, <2 x double> %0)
28 declare <2 x double> @llvm.ppc.vsx.xvdivdp(<2 x double>, <2 x double>)
29 declare <4 x float> @llvm.ppc.vsx.xvdivsp(<4 x float>, <4 x float>)
H A Ddform-pair-load-store.ll11 declare <256 x i1> @llvm.ppc.vsx.lxvp(i8*)
12 declare void @llvm.ppc.vsx.stxvp(<256 x i1>, i8*)
81 %3 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* %2)
84 %5 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* %4)
87 %7 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* %6)
90 %9 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* %8)
92 tail call void @llvm.ppc.vsx.stxvp(<256 x i1> %3, i8* %10)
94 tail call void @llvm.ppc.vsx.stxvp(<256 x i1> %5, i8* %11)
96 tail call void @llvm.ppc.vsx.stxvp(<256 x i1> %7, i8* %12)
98 tail call void @llvm.ppc.vsx.stxvp(<256 x i1> %9, i8* %13)
H A Dpaired-vector-intrinsics.ll124 %1 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* %0)
126 tail call void @llvm.ppc.vsx.stxvp(<256 x i1> %1, i8* %2)
130 declare <256 x i1> @llvm.ppc.vsx.lxvp(i8*)
131 declare void @llvm.ppc.vsx.stxvp(<256 x i1>, i8*)
160 %2 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* %1)
163 tail call void @llvm.ppc.vsx.stxvp(<256 x i1> %2, i8* %4)
194 %2 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* %1)
228 %2 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* %1)
262 %2 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* %1)
296 %2 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* %1)
[all …]
H A Dmcm-4.ll2 ; RUN: -fast-isel=false -mattr=-vsx <%s | FileCheck -check-prefix=MEDIUM %s
4 ; RUN: -fast-isel=false -mattr=+vsx <%s | FileCheck -check-prefix=MEDIUM-VSX %s
6 ; RUN: -fast-isel=false -mattr=-vsx <%s | FileCheck -check-prefix=LARGE %s
8 ; RUN: -fast-isel=false -mattr=+vsx <%s | FileCheck -check-prefix=LARGE-VSX %s
10 ; RUN: -fast-isel=false -mattr=+vsx <%s | FileCheck -check-prefix=MEDIUM-P9 %s
12 ; RUN: -fast-isel=false -mattr=+vsx <%s | FileCheck -check-prefix=LARGE-P9 %s
H A Dvrspill.ll1 ; RUN: llc -O0 -mtriple=powerpc-unknown-linux-gnu -mattr=+altivec -mattr=-vsx -verify-machineinstrs…
2 ; RUN: llc -O0 -mtriple=powerpc64-unknown-linux-gnu -mattr=+altivec -mattr=-vsx -verify-machineinst…
3 ; RUN: llc -O0 -mtriple=powerpc64-unknown-linux-gnu -mattr=+altivec -mattr=+vsx -verify-machineinst…
H A Dmore-dq-form-prepare.ll479 %55 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* nonnull %x_ix_dim_0_)
481 %56 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* nonnull %a_ix_dim_1_)
483 %57 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* nonnull %a_ix_dim_1_29)
528 %84 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* %83)
530 %86 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* %85)
532 %88 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* %87)
534 %90 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* %89)
536 %92 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* %91)
538 %94 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* %93)
540 %96 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* %95)
[all …]
H A Dfold_swtest_br.ll6 declare i32 @llvm.ppc.vsx.xvtsqrtdp(<2 x double>)
22 %0 = tail call i32 @llvm.ppc.vsx.xvtsqrtdp(<2 x double> %input)
49 %0 = tail call i32 @llvm.ppc.vsx.xvtsqrtdp(<2 x double> %input)
76 %0 = tail call i32 @llvm.ppc.vsx.xvtsqrtdp(<2 x double> %input)
103 %0 = tail call i32 @llvm.ppc.vsx.xvtsqrtdp(<2 x double> %input)
130 %0 = tail call i32 @llvm.ppc.vsx.xvtsqrtdp(<2 x double> %input)
166 %0 = tail call i32 @llvm.ppc.vsx.xvtsqrtdp(<2 x double> %input)
193 %0 = tail call i32 @llvm.ppc.vsx.xvtsqrtdp(<2 x double> %input)
H A Dloop-p10-pair-prepare.ll84 %1 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* %0)
85 %2 = tail call { <16 x i8>, <16 x i8> } @llvm.ppc.vsx.disassemble.pair(<256 x i1> %1)
89 %4 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* %3)
90 %5 = tail call { <16 x i8>, <16 x i8> } @llvm.ppc.vsx.disassemble.pair(<256 x i1> %4)
113 declare <256 x i1> @llvm.ppc.vsx.lxvp(i8*)
114 declare { <16 x i8>, <16 x i8> } @llvm.ppc.vsx.disassemble.pair(<256 x i1>)
H A Dvec_mul.ll1 …hineinstrs < %s -mtriple=powerpc-unknown-linux-gnu -mattr=+altivec -mattr=-vsx -mattr=-power8-alti…
2 …neinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mattr=+altivec -mattr=-vsx -mcpu=pwr7 | FileCh…
3 …instrs < %s -mtriple=powerpc64le-unknown-linux-gnu -mattr=+altivec -mattr=-vsx -mcpu=pwr8 -mattr=-…
4 …neinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mattr=+altivec -mattr=+vsx -mcpu=pwr7 | FileCh…
5 …instrs < %s -mtriple=powerpc64le-unknown-linux-gnu -mattr=+altivec -mattr=+vsx -mcpu=pwr8 -mattr=-…
H A Dfsqrt.ll4 ; RUN: llc -verify-machineinstrs < %s -mattr=-vsx -mtriple=powerpc-unknown-linux-gnu -mattr=+fsqrt …
5 ; RUN: llc -verify-machineinstrs < %s -mattr=-vsx -mtriple=powerpc-unknown-linux-gnu -mattr=-fsqrt …
H A Dkernel-fp-round.ll2 ; RUN: -mtriple=powerpc64le-unknown-unknown -mattr=-vsx < %s | FileCheck %s
4 ; RUN: -mtriple=powerpc-unknown-unknown -mcpu=pwr6 -mattr=-vsx < %s | \
7 ; RUN: -mtriple=powerpc64-unknown-unknown -mcpu=pwr6 -mattr=-vsx < %s | \
H A Dvsx-elementary-arith.ll127 %call = call <4 x float> @llvm.ppc.vsx.xvrsqrtesp(<4 x float> %0)
139 %call = call <2 x double> @llvm.ppc.vsx.xvrsqrtedp(<2 x double> %0)
148 declare <4 x float> @llvm.ppc.vsx.xvrsqrtesp(<4 x float>)
151 declare <2 x double> @llvm.ppc.vsx.xvrsqrtedp(<2 x double>)
H A Dfma-ext.ll1 …ify-machineinstrs < %s -mtriple=ppc32-- -fp-contract=fast -mattr=-vsx -disable-ppc-vsx-fma-mutatio…
2 …triple=powerpc64-unknown-linux-gnu -fp-contract=fast -mattr=+vsx -mcpu=pwr7 -disable-ppc-vsx-fma-m…
H A D2012-10-12-bitcast.ll1 ; RUN: llc -verify-machineinstrs -mattr=-vsx -mattr=+altivec -mcpu=pwr7 < %s | FileCheck %s
2 ; RUN: llc -verify-machineinstrs -mattr=+vsx -mattr=+altivec -mcpu=pwr7 < %s | FileCheck -check-pre…
/llvm-project-15.0.7/llvm/test/Transforms/LoopUnroll/PowerPC/
H A Dp10-respect-unroll-pragma.ll12 ; CHECK-NEXT: [[I20:%.*]] = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* nonnull inttoptr (i64 -3…
13 ; CHECK-NEXT: [[I24:%.*]] = tail call { <16 x i8>, <16 x i8> } @llvm.ppc.vsx.disassemble.pair(<2…
18 ; CHECK-NEXT: [[I20_1:%.*]] = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* nonnull inttoptr (i64 …
24 ; CHECK-NEXT: [[I20_2:%.*]] = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* nonnull inttoptr (i64 …
30 ; CHECK-NEXT: [[I20_3:%.*]] = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* nonnull inttoptr (i64 …
36 ; CHECK-NEXT: [[I20_4:%.*]] = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* nonnull inttoptr (i64 …
42 ; CHECK-NEXT: [[I20_5:%.*]] = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* nonnull inttoptr (i64 …
135 %i20 = call <256 x i1> @llvm.ppc.vsx.lxvp(i8* %i19)
140 %i24 = call { <16 x i8>, <16 x i8> } @llvm.ppc.vsx.disassemble.pair(<256 x i1> %i23)
147 declare <256 x i1> @llvm.ppc.vsx.lxvp(i8*) #1
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/PowerPC/
H A Dvsx-unaligned.ll19 %2 = call <4 x i32> @llvm.ppc.vsx.lxvw4x(i8* %1)
23 call void @llvm.ppc.vsx.stxvw4x(<4 x i32> %2, i8* %4)
27 %7 = call <2 x double> @llvm.ppc.vsx.lxvd2x(i8* %6)
31 call void @llvm.ppc.vsx.stxvd2x(<2 x double> %7, i8* %9)
41 declare <4 x i32> @llvm.ppc.vsx.lxvw4x(i8*)
42 declare void @llvm.ppc.vsx.stxvw4x(<4 x i32>, i8*)
43 declare <2 x double> @llvm.ppc.vsx.lxvd2x(i8*)
44 declare void @llvm.ppc.vsx.stxvd2x(<2 x double>, i8*)
/llvm-project-15.0.7/clang/test/CodeGen/PowerPC/
H A Dbuiltins-ppc-p8vector.c34 vector signed __int128 vsx = { 1 }; variable
100 res_vsx = vec_addc(vsx, vsx); in test1()
113 res_vsx = vec_adde(vsx, vsx, vsx); in test1()
126 res_vsx = vec_addec(vsx, vsx, vsx); in test1()
1153 res_vsx = vec_sub(vsx, vsx); in test1()

12345678