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Searched refs:vsll (Results 1 – 25 of 47) sorted by relevance

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/llvm-project-15.0.7/clang/test/CodeGen/PowerPC/
H A Dbuiltins-ppc-vsx.c344 res_vsll = vec_div(vsll, vsll); in test1()
456 res_vsi = vec_pack(vsll, vsll); in test1()
677 res_vsll = vec_and(vsll, vsll); in test1()
706 res_vsll = vec_vand(vsll, vsll); in test1()
735 res_vsll = vec_andc(vsll, vsll); in test1()
864 res_vsll = vec_mul(vsll, vsll); in test1()
909 res_vsll = vec_nor(vsll, vsll); in test1()
936 res_vsll = vec_or(vsll, vsll); in test1()
1156 res_vsll = vec_vor(vsll, vsll); in test1()
1185 res_vsll = vec_xor(vsll, vsll); in test1()
[all …]
H A Dbuiltins-ppc-p8vector.c79 res_vsll = vec_add(vsll, vsll); in test1()
152 res_vsll = vec_mergee(vsll, vsll); in test1()
187 res_vbll = vec_cmpeq(vsll, vsll); in test1()
196 res_vbll = vec_cmpge(vsll, vsll); in test1()
205 res_vbll = vec_cmple(vsll, vsll); in test1()
214 res_vbll = vec_cmpgt(vsll, vsll); in test1()
223 res_vbll = vec_cmplt(vsll, vsll); in test1()
313 res_vsll = vec_eqv(vsll, vsll); in test1()
555 res_vsll = vec_max(vsll, vsll); in test1()
595 res_vsll = vec_min(vsll, vsll); in test1()
[all …]
H A Dbuiltins-ppc-xlcompat.c14 vector signed long long res_vsll, vsll = { -12345678999ll, 12345678999 }; variable
27 res_vf = vec_ctf(vsll, 4); in test()
/llvm-project-15.0.7/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/
H A Dvsll.c13 return vsll(op1, shift, vl); in test_vsll_vv_i8mf8()
22 return vsll(op1, shift, vl); in test_vsll_vx_i8mf8()
31 return vsll(op1, shift, vl); in test_vsll_vv_i8mf4()
40 return vsll(op1, shift, vl); in test_vsll_vx_i8mf4()
49 return vsll(op1, shift, vl); in test_vsll_vv_i8mf2()
58 return vsll(op1, shift, vl); in test_vsll_vx_i8mf2()
67 return vsll(op1, shift, vl); in test_vsll_vv_i8m1()
76 return vsll(op1, shift, vl); in test_vsll_vx_i8m1()
85 return vsll(op1, shift, vl); in test_vsll_vv_i8m2()
94 return vsll(op1, shift, vl); in test_vsll_vx_i8m2()
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/
H A Dvsll-rv32.ll14 ; CHECK-NEXT: vsll.vv v8, v8, v9
61 ; CHECK-NEXT: vsll.vv v8, v8, v9
108 ; CHECK-NEXT: vsll.vv v8, v8, v9
155 ; CHECK-NEXT: vsll.vv v8, v8, v9
202 ; CHECK-NEXT: vsll.vv v8, v8, v10
249 ; CHECK-NEXT: vsll.vv v8, v8, v12
296 ; CHECK-NEXT: vsll.vv v8, v8, v16
344 ; CHECK-NEXT: vsll.vv v8, v8, v9
391 ; CHECK-NEXT: vsll.vv v8, v8, v9
438 ; CHECK-NEXT: vsll.vv v8, v8, v9
[all …]
H A Dvsll-rv64.ll14 ; CHECK-NEXT: vsll.vv v8, v8, v9
61 ; CHECK-NEXT: vsll.vv v8, v8, v9
108 ; CHECK-NEXT: vsll.vv v8, v8, v9
155 ; CHECK-NEXT: vsll.vv v8, v8, v9
202 ; CHECK-NEXT: vsll.vv v8, v8, v10
249 ; CHECK-NEXT: vsll.vv v8, v8, v12
296 ; CHECK-NEXT: vsll.vv v8, v8, v16
344 ; CHECK-NEXT: vsll.vv v8, v8, v9
391 ; CHECK-NEXT: vsll.vv v8, v8, v9
438 ; CHECK-NEXT: vsll.vv v8, v8, v9
[all …]
H A Dbswap-sdnode.ll10 ; CHECK-NEXT: vsll.vi v8, v8, 8
23 ; CHECK-NEXT: vsll.vi v8, v8, 8
36 ; CHECK-NEXT: vsll.vi v8, v8, 8
49 ; CHECK-NEXT: vsll.vi v8, v8, 8
62 ; CHECK-NEXT: vsll.vi v8, v8, 8
75 ; CHECK-NEXT: vsll.vi v8, v8, 8
93 ; RV32-NEXT: vsll.vi v10, v8, 8
96 ; RV32-NEXT: vsll.vi v8, v8, 24
110 ; RV64-NEXT: vsll.vi v10, v8, 8
113 ; RV64-NEXT: vsll.vi v8, v8, 24
[all …]
H A Dbitreverse-sdnode.ll10 ; CHECK-NEXT: vsll.vi v9, v9, 4
18 ; CHECK-NEXT: vsll.vi v8, v8, 2
37 ; CHECK-NEXT: vsll.vi v9, v9, 4
45 ; CHECK-NEXT: vsll.vi v8, v8, 2
64 ; CHECK-NEXT: vsll.vi v9, v9, 4
72 ; CHECK-NEXT: vsll.vi v8, v8, 2
91 ; CHECK-NEXT: vsll.vi v9, v9, 4
99 ; CHECK-NEXT: vsll.vi v8, v8, 2
199 ; RV32-NEXT: vsll.vi v8, v8, 8
206 ; RV32-NEXT: vsll.vi v8, v8, 4
[all …]
H A Dfixed-vectors-bswap.ll13 ; CHECK-NEXT: vsll.vi v8, v8, 8
36 ; RV32-NEXT: vsll.vi v10, v8, 8
39 ; RV32-NEXT: vsll.vi v8, v8, 24
55 ; RV64-NEXT: vsll.vi v10, v8, 8
58 ; RV64-NEXT: vsll.vi v8, v8, 24
103 ; RV32-NEXT: vsll.vi v11, v8, 8
109 ; RV32-NEXT: vsll.vi v12, v8, 24
112 ; RV32-NEXT: vsll.vx v11, v8, a2
118 ; RV32-NEXT: vsll.vx v8, v8, a1
146 ; RV64-NEXT: vsll.vi v10, v8, 8
[all …]
H A Dfixed-vectors-bitreverse.ll13 ; RV32-NEXT: vsll.vi v8, v8, 8
20 ; RV32-NEXT: vsll.vi v8, v8, 4
27 ; RV32-NEXT: vsll.vi v8, v8, 2
44 ; RV64-NEXT: vsll.vi v8, v8, 8
51 ; RV64-NEXT: vsll.vi v8, v8, 4
58 ; RV64-NEXT: vsll.vi v8, v8, 2
88 ; RV32-NEXT: vsll.vi v10, v8, 8
99 ; RV32-NEXT: vsll.vi v8, v8, 4
106 ; RV32-NEXT: vsll.vi v8, v8, 2
139 ; RV64-NEXT: vsll.vi v8, v8, 4
[all …]
H A Dfixed-vectors-vshl-vp.ll38 ; CHECK-NEXT: vsll.vv v8, v8, v9
62 ; CHECK-NEXT: vsll.vx v8, v8, a0
88 ; CHECK-NEXT: vsll.vi v8, v8, 3
126 ; CHECK-NEXT: vsll.vv v8, v8, v9
150 ; CHECK-NEXT: vsll.vx v8, v8, a0
176 ; CHECK-NEXT: vsll.vi v8, v8, 3
202 ; CHECK-NEXT: vsll.vv v8, v8, v9
226 ; CHECK-NEXT: vsll.vx v8, v8, a0
252 ; CHECK-NEXT: vsll.vi v8, v8, 3
328 ; CHECK-NEXT: vsll.vi v8, v8, 3
[all …]
H A Dvshl-sdnode.ll9 ; CHECK-NEXT: vsll.vx v8, v8, a0
21 ; CHECK-NEXT: vsll.vi v8, v8, 6
33 ; CHECK-NEXT: vsll.vx v8, v8, a0
45 ; CHECK-NEXT: vsll.vi v8, v8, 6
57 ; CHECK-NEXT: vsll.vx v8, v8, a0
69 ; CHECK-NEXT: vsll.vi v8, v8, 6
81 ; CHECK-NEXT: vsll.vx v8, v8, a0
93 ; CHECK-NEXT: vsll.vi v8, v8, 6
117 ; CHECK-NEXT: vsll.vi v8, v8, 6
141 ; CHECK-NEXT: vsll.vi v8, v8, 6
[all …]
H A Dvshl-vp.ll41 ; CHECK-NEXT: vsll.vv v8, v8, v9
65 ; CHECK-NEXT: vsll.vx v8, v8, a0
91 ; CHECK-NEXT: vsll.vi v8, v8, 3
117 ; CHECK-NEXT: vsll.vv v8, v8, v9
141 ; CHECK-NEXT: vsll.vx v8, v8, a0
167 ; CHECK-NEXT: vsll.vi v8, v8, 3
193 ; CHECK-NEXT: vsll.vv v8, v8, v9
217 ; CHECK-NEXT: vsll.vx v8, v8, a0
243 ; CHECK-NEXT: vsll.vi v8, v8, 3
331 ; CHECK-NEXT: vsll.vi v8, v8, 3
[all …]
H A Dfixed-vectors-vpgather.ll703 ; RV32-NEXT: vsll.vi v8, v10, 2
726 ; RV32-NEXT: vsll.vi v8, v10, 2
750 ; RV32-NEXT: vsll.vi v8, v10, 2
774 ; RV32-NEXT: vsll.vi v8, v10, 2
797 ; RV32-NEXT: vsll.vi v8, v10, 2
821 ; RV32-NEXT: vsll.vi v8, v10, 2
844 ; RV32-NEXT: vsll.vi v8, v8, 2
1166 ; RV32-NEXT: vsll.vi v8, v8, 3
1176 ; RV64-NEXT: vsll.vi v8, v8, 3
1581 ; RV32-NEXT: vsll.vi v8, v8, 2
[all …]
H A Dvpscatter-sdnode.ll539 ; RV32-NEXT: vsll.vi v12, v16, 2
548 ; RV64-NEXT: vsll.vi v16, v16, 2
562 ; RV32-NEXT: vsll.vi v12, v16, 2
571 ; RV64-NEXT: vsll.vi v16, v16, 2
586 ; RV32-NEXT: vsll.vi v12, v16, 2
595 ; RV64-NEXT: vsll.vi v16, v16, 2
2198 ; RV64-NEXT: vsll.vi v8, v8, 3
2233 ; RV32-NEXT: vsll.vi v8, v8, 3
2290 ; RV64-NEXT: vsll.vi v8, v8, 3
2349 ; RV32-NEXT: vsll.vi v8, v8, 3
[all …]
H A Dfixed-vectors-vpscatter.ll521 ; RV32-NEXT: vsll.vi v10, v12, 2
530 ; RV64-NEXT: vsll.vi v12, v12, 2
544 ; RV32-NEXT: vsll.vi v10, v12, 2
553 ; RV64-NEXT: vsll.vi v12, v12, 2
568 ; RV32-NEXT: vsll.vi v10, v12, 2
577 ; RV64-NEXT: vsll.vi v12, v12, 2
592 ; RV32-NEXT: vsll.vi v10, v12, 2
601 ; RV64-NEXT: vsll.vi v12, v12, 2
615 ; RV32-NEXT: vsll.vi v10, v12, 2
1993 ; RV64-NEXT: vsll.vi v8, v8, 3
[all …]
H A Dvpgather-sdnode.ll775 ; RV32-NEXT: vsll.vi v8, v12, 2
798 ; RV32-NEXT: vsll.vi v8, v12, 2
822 ; RV32-NEXT: vsll.vi v8, v12, 2
846 ; RV32-NEXT: vsll.vi v8, v12, 2
869 ; RV32-NEXT: vsll.vi v8, v12, 2
893 ; RV32-NEXT: vsll.vi v8, v12, 2
916 ; RV32-NEXT: vsll.vi v8, v8, 2
1257 ; RV32-NEXT: vsll.vi v8, v8, 3
1267 ; RV64-NEXT: vsll.vi v8, v8, 3
1711 ; RV32-NEXT: vsll.vi v8, v8, 2
[all …]
H A Dmscatter-sdnode.ll551 ; RV32-NEXT: vsll.vi v12, v16, 2
559 ; RV64-NEXT: vsll.vi v16, v16, 2
573 ; RV32-NEXT: vsll.vi v12, v16, 2
581 ; RV64-NEXT: vsll.vi v16, v16, 2
596 ; RV32-NEXT: vsll.vi v12, v16, 2
604 ; RV64-NEXT: vsll.vi v16, v16, 2
619 ; RV32-NEXT: vsll.vi v12, v16, 2
627 ; RV64-NEXT: vsll.vi v16, v16, 2
641 ; RV32-NEXT: vsll.vi v12, v16, 2
1904 ; RV64-NEXT: vsll.vi v8, v8, 3
[all …]
H A Dmgather-sdnode.ll736 ; RV32-NEXT: vsll.vi v8, v16, 2
760 ; RV32-NEXT: vsll.vi v8, v16, 2
785 ; RV32-NEXT: vsll.vi v8, v16, 2
810 ; RV32-NEXT: vsll.vi v8, v16, 2
834 ; RV32-NEXT: vsll.vi v8, v16, 2
859 ; RV32-NEXT: vsll.vi v8, v16, 2
883 ; RV32-NEXT: vsll.vi v8, v8, 2
1170 ; RV32-NEXT: vsll.vi v8, v8, 3
1247 ; RV32-NEXT: vsll.vi v8, v8, 3
1258 ; RV64-NEXT: vsll.vi v8, v8, 3
[all …]
H A Dfshr-fshl.ll15 ; CHECK-NEXT: vsll.vv v8, v8, v10
28 ; CHECK-NEXT: vsll.vv v8, v8, v11
/llvm-project-15.0.7/llvm/test/CodeGen/VE/VELIntrinsics/
H A Dvsll.ll16 ; CHECK-NEXT: vsll %v0, %v0, %v1
23 declare <256 x double> @llvm.ve.vl.vsll.vvvl(<256 x double>, <256 x double>, i32)
31 ; CHECK-NEXT: vsll %v2, %v0, %v1
49 ; CHECK-NEXT: vsll %v0, %v0, %s0
56 declare <256 x double> @llvm.ve.vl.vsll.vvsl(<256 x double>, i64, i32)
64 ; CHECK-NEXT: vsll %v1, %v0, %s0
82 ; CHECK-NEXT: vsll %v0, %v0, 8
94 ; CHECK-NEXT: vsll %v1, %v0, 8
109 ; CHECK-NEXT: vsll %v2, %v0, %v1, %vm1
127 ; CHECK-NEXT: vsll %v1, %v0, %s0, %vm1
[all …]
/llvm-project-15.0.7/llvm/test/MC/VE/
H A DVSLL.s6 # CHECK-INST: vsll %v11, %v22, %s20
8 vsll %v11, %v22, %s20 label
10 # CHECK-INST: vsll %vix, %vix, %vix
12 vsll %vix, %vix, %vix label
/llvm-project-15.0.7/llvm/test/MC/RISCV/rvv/
H A Dshift.s11 vsll.vv v8, v4, v20, v0.t
12 # CHECK-INST: vsll.vv v8, v4, v20, v0.t
17 vsll.vv v8, v4, v20
18 # CHECK-INST: vsll.vv v8, v4, v20
23 vsll.vx v8, v4, a0, v0.t
24 # CHECK-INST: vsll.vx v8, v4, a0, v0.t
29 vsll.vx v8, v4, a0
30 # CHECK-INST: vsll.vx v8, v4, a0
35 vsll.vi v8, v4, 31, v0.t
41 vsll.vi v8, v4, 31
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A Dvsx-ldst-builtin-le.ll19 @vsll = global <2 x i64> <i64 255, i64 -937>, align 16
53 %4 = call <2 x double> @llvm.ppc.vsx.lxvd2x(i8* bitcast (<2 x i64>* @vsll to i8*))
92 %13 = load <2 x i64>, <2 x i64>* @vsll, align 16
H A Dvsx-ldst.ll29 @vsll = global <2 x i64> <i64 255, i64 -937>, align 16
45 %3 = load <2 x double>, <2 x double>* bitcast (<2 x i64>* @vsll to <2 x double>*), align 16

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