Home
last modified time | relevance | path

Searched refs:vs7 (Results 1 – 21 of 21) sorted by relevance

/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A Dvec_conv_fp_to_i_8byte_elts.ll153 ; CHECK-P8-NEXT: xvcvdpuxds vs7, vs7
174 ; CHECK-P9-NEXT: lxv vs7, 0(r4)
175 ; CHECK-P9-NEXT: xvcvdpuxds vs7, vs7
189 ; CHECK-P9-NEXT: stxv vs7, 0(r3)
202 ; CHECK-BE-NEXT: lxv vs7, 0(r4)
203 ; CHECK-BE-NEXT: xvcvdpuxds vs7, vs7
217 ; CHECK-BE-NEXT: stxv vs7, 0(r3)
367 ; CHECK-P8-NEXT: xvcvdpsxds vs7, vs7
388 ; CHECK-P9-NEXT: lxv vs7, 0(r4)
389 ; CHECK-P9-NEXT: xvcvdpsxds vs7, vs7
[all …]
H A Dvec_conv_fp32_to_i64_elts.ll202 ; CHECK-P8-NEXT: xvcvspdp vs7, vs7
251 ; CHECK-P9-NEXT: xvcvspdp vs7, vs7
259 ; CHECK-P9-NEXT: xvcvdpuxds vs7, vs7
262 ; CHECK-P9-NEXT: stxv vs7, 96(r3)
291 ; CHECK-BE-NEXT: xvcvspdp vs7, vs7
299 ; CHECK-BE-NEXT: xvcvdpuxds vs7, vs7
507 ; CHECK-P8-NEXT: xvcvspdp vs7, vs7
556 ; CHECK-P9-NEXT: xvcvspdp vs7, vs7
564 ; CHECK-P9-NEXT: xvcvdpuxds vs7, vs7
596 ; CHECK-BE-NEXT: xvcvspdp vs7, vs7
[all …]
H A Dvec_conv_fp64_to_i32_elts.ll177 ; CHECK-P8-NEXT: lxvd2x vs7, r4, r7
184 ; CHECK-P8-NEXT: xxmrghd vs1, vs8, vs7
205 ; CHECK-P9-NEXT: lxv vs7, 16(r4)
218 ; CHECK-P9-NEXT: xvcvdpuxws v4, vs7
241 ; CHECK-BE-NEXT: lxv vs7, 0(r4)
254 ; CHECK-BE-NEXT: xvcvdpuxws v4, vs7
445 ; CHECK-P8-NEXT: lxvd2x vs7, r4, r7
473 ; CHECK-P9-NEXT: lxv vs7, 16(r4)
486 ; CHECK-P9-NEXT: xvcvdpsxws v4, vs7
509 ; CHECK-BE-NEXT: lxv vs7, 0(r4)
[all …]
H A Dvec_conv_i_to_fp_8byte_elts.ll145 ; CHECK-P8-NEXT: lxvd2x vs7, 0, r4
153 ; CHECK-P8-NEXT: xvcvuxddp vs7, vs7
161 ; CHECK-P8-NEXT: stxvd2x vs7, 0, r3
181 ; CHECK-P9-NEXT: xvcvuxddp vs7, v2
182 ; CHECK-P9-NEXT: stxv vs7, 112(r3)
209 ; CHECK-BE-NEXT: xvcvuxddp vs7, v2
210 ; CHECK-BE-NEXT: stxv vs7, 112(r3)
359 ; CHECK-P8-NEXT: lxvd2x vs7, 0, r4
367 ; CHECK-P8-NEXT: xvcvsxddp vs7, vs7
395 ; CHECK-P9-NEXT: xvcvsxddp vs7, v2
[all …]
H A Dvec_conv_i32_to_fp64_elts.ll182 ; CHECK-P8-NEXT: xvcvuxwdp vs7, v3
193 ; CHECK-P8-NEXT: xxswapd vs3, vs7
225 ; CHECK-P9-NEXT: xvcvuxwdp vs7, v2
230 ; CHECK-P9-NEXT: stxv vs7, 96(r3)
257 ; CHECK-BE-NEXT: xvcvuxwdp vs7, v2
262 ; CHECK-BE-NEXT: stxv vs7, 96(r3)
442 ; CHECK-P8-NEXT: xvcvsxwdp vs7, v3
453 ; CHECK-P8-NEXT: xxswapd vs3, vs7
485 ; CHECK-P9-NEXT: xvcvsxwdp vs7, v2
490 ; CHECK-P9-NEXT: stxv vs7, 96(r3)
[all …]
H A Dvec_conv_fp64_to_i8_elts.ll319 ; CHECK-P8-NEXT: lxvd2x vs7, r3, r4
331 ; CHECK-P8-NEXT: xxswapd vs7, vs7
395 ; CHECK-P9-NEXT: lxv vs7, 0(r3)
400 ; CHECK-P9-NEXT: xxswapd vs7, vs7
478 ; CHECK-BE-NEXT: lxv vs7, 112(r3)
483 ; CHECK-BE-NEXT: xxswapd vs7, vs7
886 ; CHECK-P8-NEXT: xxswapd vs7, vs7
950 ; CHECK-P9-NEXT: lxv vs7, 0(r3)
955 ; CHECK-P9-NEXT: xxswapd vs7, vs7
1033 ; CHECK-BE-NEXT: lxv vs7, 112(r3)
[all …]
H A Dppc64-acc-regalloc.ll59 ; CHECK-NEXT: xxlor vs7, v7, v7
135 ; TRACKLIVE-NEXT: xxlxor vs7, vs7, vs7
144 ; TRACKLIVE-NEXT: xvmaddadp vs7, vs0, v5
151 ; TRACKLIVE-NEXT: xvmaddadp vs7, v2, v2
H A Dvector-reduce-fadd.ll2295 ; PWR9LE-NEXT: lxv vs7, 416(r1)
2371 ; PWR9LE-NEXT: xxswapd vs9, vs7
2377 ; PWR9LE-NEXT: xxswapd vs7, vs5
2413 ; PWR9BE-NEXT: lxv vs7, 432(r1)
2491 ; PWR9BE-NEXT: xxswapd vs7, vs7
2729 ; PWR10BE-NEXT: xxswapd vs7, vs7
2776 ; PWR9LE-NEXT: lxv vs7, 432(r1)
2856 ; PWR9LE-NEXT: xxswapd vs8, vs7
2859 ; PWR9LE-NEXT: xxswapd vs7, vs6
2977 ; PWR9BE-NEXT: xxswapd vs7, vs7
[all …]
H A Dvec_conv_i16_to_fp64_elts.ll265 ; CHECK-P8-NEXT: xvcvuxddp vs7, v1
275 ; CHECK-P8-NEXT: xxswapd vs2, vs7
323 ; CHECK-P9-NEXT: xvcvuxddp vs7, v2
326 ; CHECK-P9-NEXT: stxv vs7, 112(r3)
366 ; CHECK-BE-NEXT: xvcvuxddp vs7, v2
369 ; CHECK-BE-NEXT: stxv vs7, 112(r3)
685 ; CHECK-P8-NEXT: xvcvsxddp vs7, v6
695 ; CHECK-P8-NEXT: xxswapd vs2, vs7
749 ; CHECK-P9-NEXT: xvcvsxddp vs7, v2
751 ; CHECK-P9-NEXT: stxv vs7, 112(r3)
[all …]
H A Dvec_conv_i8_to_fp64_elts.ll280 ; CHECK-P8-NEXT: xvcvuxddp vs7, v5
293 ; CHECK-P8-NEXT: xxswapd vs2, vs7
352 ; CHECK-P9-NEXT: xvcvuxddp vs7, v2
353 ; CHECK-P9-NEXT: stxv vs7, 112(r3)
405 ; CHECK-BE-NEXT: xvcvuxddp vs7, v2
406 ; CHECK-BE-NEXT: stxv vs7, 112(r3)
733 ; CHECK-P8-NEXT: xvcvsxddp vs7, v4
747 ; CHECK-P8-NEXT: xxswapd vs2, vs7
811 ; CHECK-P9-NEXT: xvcvsxddp vs7, v2
812 ; CHECK-P9-NEXT: stxv vs7, 112(r3)
[all …]
H A Dmma-intrinsics.ll306 ; CHECK-NEXT: stxv vs7, 0(r3)
323 ; CHECK-BE-NEXT: stxv vs7, 48(r3)
354 ; CHECK-NEXT: stxv vs7, 0(r3)
371 ; CHECK-BE-NEXT: stxv vs7, 48(r3)
430 ; CHECK-NEXT: stxv vs7, 64(r8)
478 ; CHECK-BE-NEXT: stxv vs7, 112(r8)
565 ; CHECK-NEXT: stxv vs7, 32(r1)
598 ; CHECK-BE-NEXT: stxv vs7, 160(r1)
H A Dvec_conv_i64_to_fp32_elts.ll204 ; CHECK-P8-NEXT: xvcvuxdsp vs7, v5
213 ; CHECK-P8-NEXT: xxsldwi v7, vs7, vs7, 3
496 ; CHECK-P8-NEXT: xvcvsxdsp vs7, v5
505 ; CHECK-P8-NEXT: xxsldwi v7, vs7, vs7, 3
H A Dvec-trunc2.ll54 ; CHECK-BE-NEXT: lxvw4x vs7, 0, r3
62 ; CHECK-BE-NEXT: xxmrghw vs3, vs7, vs6
H A Dvector-reduce-fmin.ll1062 ; PWR9LE-NEXT: xvmindp vs7, v4, v12
1067 ; PWR9LE-NEXT: xvmindp vs0, vs7, vs0
1089 ; PWR9BE-NEXT: xvmindp vs7, v4, v12
1094 ; PWR9BE-NEXT: xvmindp vs0, vs7, vs0
1113 ; PWR10LE-NEXT: xvmindp vs7, v4, v12
1120 ; PWR10LE-NEXT: xvmindp vs0, vs7, vs0
1140 ; PWR10BE-NEXT: xvmindp vs7, v4, v12
1147 ; PWR10BE-NEXT: xvmindp vs0, vs7, vs0
H A Dvector-reduce-fmax.ll1062 ; PWR9LE-NEXT: xvmaxdp vs7, v4, v12
1067 ; PWR9LE-NEXT: xvmaxdp vs0, vs7, vs0
1089 ; PWR9BE-NEXT: xvmaxdp vs7, v4, v12
1094 ; PWR9BE-NEXT: xvmaxdp vs0, vs7, vs0
1113 ; PWR10LE-NEXT: xvmaxdp vs7, v4, v12
1120 ; PWR10LE-NEXT: xvmaxdp vs0, vs7, vs0
1140 ; PWR10BE-NEXT: xvmaxdp vs7, v4, v12
1147 ; PWR10BE-NEXT: xvmaxdp vs0, vs7, vs0
H A Dvec_conv_fp32_to_i16_elts.ll180 ; CHECK-P8-NEXT: xxsldwi vs7, v3, v3, 1
187 ; CHECK-P8-NEXT: xscvspdpn f7, vs7
360 ; CHECK-P8-NEXT: xxsldwi vs7, v0, v0, 3
399 ; CHECK-P8-NEXT: xscvspdpn f7, vs7
812 ; CHECK-P8-NEXT: xxsldwi vs7, v3, v3, 1
819 ; CHECK-P8-NEXT: xscvspdpn f7, vs7
992 ; CHECK-P8-NEXT: xxsldwi vs7, v0, v0, 3
1031 ; CHECK-P8-NEXT: xscvspdpn f7, vs7
H A Dvec_conv_fp64_to_i16_elts.ll303 ; CHECK-P8-NEXT: lxvd2x vs7, r4, r7
316 ; CHECK-P8-NEXT: xxswapd vs7, vs7
850 ; CHECK-P8-NEXT: lxvd2x vs7, r4, r7
863 ; CHECK-P8-NEXT: xxswapd vs7, vs7
H A Dspill-vec-pair.ll158 …ffect "nop", "~{memory},~{vs0},~{vs1},~{vs2},~{vs3},~{vs4},~{vs5},~{vs6},~{vs7},~{vs8},~{vs9},~{vs…
H A Dvec_conv_fp32_to_i8_elts.ll189 ; CHECK-P8-NEXT: xxsldwi vs7, v3, v3, 1
196 ; CHECK-P8-NEXT: xscvspdpn f7, vs7
829 ; CHECK-P8-NEXT: xxsldwi vs7, v3, v3, 1
836 ; CHECK-P8-NEXT: xscvspdpn f7, vs7
/llvm-project-15.0.7/lldb/source/Plugins/Process/Utility/
H A DRegisterInfos_ppc64le.h213 DEFINE_VSX(vs7, LLDB_INVALID_REGNUM), \
398 uint32_t vs7[4]; member
/llvm-project-15.0.7/llvm/test/MC/PowerPC/
H A Dvsx.s6 xxswapd %vs7, %vs63