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Searched refs:vs6 (Results 1 – 20 of 20) sorted by relevance

/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A Dvec_conv_fp_to_i_8byte_elts.ll152 ; CHECK-P8-NEXT: xvcvdpuxds vs6, vs6
173 ; CHECK-P9-NEXT: lxv vs6, 16(r4)
176 ; CHECK-P9-NEXT: xvcvdpuxds vs6, vs6
188 ; CHECK-P9-NEXT: stxv vs6, 16(r3)
201 ; CHECK-BE-NEXT: lxv vs6, 16(r4)
204 ; CHECK-BE-NEXT: xvcvdpuxds vs6, vs6
216 ; CHECK-BE-NEXT: stxv vs6, 16(r3)
366 ; CHECK-P8-NEXT: xvcvdpsxds vs6, vs6
387 ; CHECK-P9-NEXT: lxv vs6, 16(r4)
390 ; CHECK-P9-NEXT: xvcvdpsxds vs6, vs6
[all …]
H A Dvec_conv_fp32_to_i64_elts.ll201 ; CHECK-P8-NEXT: xvcvspdp vs6, vs6
249 ; CHECK-P9-NEXT: xvcvspdp vs6, vs6
257 ; CHECK-P9-NEXT: xvcvdpuxds vs6, vs6
264 ; CHECK-P9-NEXT: stxv vs6, 64(r3)
289 ; CHECK-BE-NEXT: xvcvspdp vs6, vs6
297 ; CHECK-BE-NEXT: xvcvdpuxds vs6, vs6
506 ; CHECK-P8-NEXT: xvcvspdp vs6, vs6
554 ; CHECK-P9-NEXT: xvcvspdp vs6, vs6
562 ; CHECK-P9-NEXT: xvcvdpuxds vs6, vs6
594 ; CHECK-BE-NEXT: xvcvspdp vs6, vs6
[all …]
H A Dvec_conv_fp64_to_i32_elts.ll174 ; CHECK-P8-NEXT: lxvd2x vs6, r4, r8
204 ; CHECK-P9-NEXT: lxv vs6, 0(r4)
209 ; CHECK-P9-NEXT: xxmrghd vs6, vs7, vs6
217 ; CHECK-P9-NEXT: xvcvdpuxws v3, vs6
240 ; CHECK-BE-NEXT: lxv vs6, 16(r4)
245 ; CHECK-BE-NEXT: xxmrghd vs6, vs7, vs6
253 ; CHECK-BE-NEXT: xvcvdpuxws v3, vs6
472 ; CHECK-P9-NEXT: lxv vs6, 0(r4)
477 ; CHECK-P9-NEXT: xxmrghd vs6, vs7, vs6
508 ; CHECK-BE-NEXT: lxv vs6, 16(r4)
[all …]
H A Dvec_conv_i_to_fp_8byte_elts.ll144 ; CHECK-P8-NEXT: lxvd2x vs6, r4, r11
152 ; CHECK-P8-NEXT: xvcvuxddp vs6, vs6
180 ; CHECK-P9-NEXT: xvcvuxddp vs6, v3
183 ; CHECK-P9-NEXT: stxv vs6, 96(r3)
208 ; CHECK-BE-NEXT: xvcvuxddp vs6, v3
211 ; CHECK-BE-NEXT: stxv vs6, 96(r3)
366 ; CHECK-P8-NEXT: xvcvsxddp vs6, vs6
394 ; CHECK-P9-NEXT: xvcvsxddp vs6, v3
397 ; CHECK-P9-NEXT: stxv vs6, 96(r3)
422 ; CHECK-BE-NEXT: xvcvsxddp vs6, v3
[all …]
H A Dvec_conv_i32_to_fp64_elts.ll180 ; CHECK-P8-NEXT: xvcvuxwdp vs6, v2
191 ; CHECK-P8-NEXT: xxswapd vs5, vs6
219 ; CHECK-P9-NEXT: xvcvuxwdp vs6, v2
227 ; CHECK-P9-NEXT: stxv vs6, 64(r3)
251 ; CHECK-BE-NEXT: xvcvuxwdp vs6, v2
259 ; CHECK-BE-NEXT: stxv vs6, 64(r3)
440 ; CHECK-P8-NEXT: xvcvsxwdp vs6, v2
451 ; CHECK-P8-NEXT: xxswapd vs5, vs6
479 ; CHECK-P9-NEXT: xvcvsxwdp vs6, v2
487 ; CHECK-P9-NEXT: stxv vs6, 64(r3)
[all …]
H A Dvector-reduce-fadd.ll2494 ; PWR9BE-NEXT: xxswapd vs6, vs6
2732 ; PWR10BE-NEXT: xxswapd vs6, vs6
2980 ; PWR9BE-NEXT: xxswapd vs6, vs6
3220 ; PWR10BE-NEXT: xxswapd vs6, vs6
3277 ; PWR9LE-NEXT: xvadddp vs6, vs7, vs6
3290 ; PWR9LE-NEXT: xvadddp vs6, vs7, vs6
3336 ; PWR9BE-NEXT: xvadddp vs6, vs7, vs6
3349 ; PWR9BE-NEXT: xvadddp vs6, vs7, vs6
3383 ; PWR10LE-NEXT: xvadddp vs6, vs7, vs6
3407 ; PWR10LE-NEXT: xvadddp vs6, vs7, vs6
[all …]
H A Dvec_conv_i16_to_fp64_elts.ll263 ; CHECK-P8-NEXT: xvcvuxddp vs6, v6
276 ; CHECK-P8-NEXT: xxswapd vs3, vs6
322 ; CHECK-P9-NEXT: xvcvuxddp vs6, v3
327 ; CHECK-P9-NEXT: stxv vs6, 96(r3)
365 ; CHECK-BE-NEXT: xvcvuxddp vs6, v3
370 ; CHECK-BE-NEXT: stxv vs6, 96(r3)
682 ; CHECK-P8-NEXT: xvcvsxddp vs6, v1
692 ; CHECK-P8-NEXT: xxswapd vs3, vs6
745 ; CHECK-P9-NEXT: xvcvsxddp vs6, v2
750 ; CHECK-P9-NEXT: stxv vs6, 96(r3)
[all …]
H A Dvec_conv_i8_to_fp64_elts.ll278 ; CHECK-P8-NEXT: xvcvuxddp vs6, v3
290 ; CHECK-P8-NEXT: xxswapd vs3, vs6
348 ; CHECK-P9-NEXT: xvcvuxddp vs6, v3
351 ; CHECK-P9-NEXT: stxv vs6, 96(r3)
401 ; CHECK-BE-NEXT: xvcvuxddp vs6, v3
404 ; CHECK-BE-NEXT: stxv vs6, 96(r3)
732 ; CHECK-P8-NEXT: xvcvsxddp vs6, v3
744 ; CHECK-P8-NEXT: xxswapd vs3, vs6
806 ; CHECK-P9-NEXT: xvcvsxddp vs6, v3
809 ; CHECK-P9-NEXT: stxv vs6, 96(r3)
[all …]
H A Dmma-intrinsics.ll305 ; CHECK-NEXT: stxv vs6, 16(r3)
324 ; CHECK-BE-NEXT: stxv vs6, 32(r3)
353 ; CHECK-NEXT: stxv vs6, 16(r3)
372 ; CHECK-BE-NEXT: stxv vs6, 32(r3)
429 ; CHECK-NEXT: stxv vs6, 80(r8)
479 ; CHECK-BE-NEXT: stxv vs6, 96(r8)
564 ; CHECK-NEXT: stxv vs6, 48(r1)
597 ; CHECK-BE-NEXT: stxv vs6, 144(r1)
H A Dvec_conv_fp64_to_i8_elts.ll396 ; CHECK-P9-NEXT: lxv vs6, 16(r3)
410 ; CHECK-P9-NEXT: xxswapd vs6, vs6
487 ; CHECK-BE-NEXT: lxv vs6, 96(r3)
496 ; CHECK-BE-NEXT: xxswapd vs6, vs6
951 ; CHECK-P9-NEXT: lxv vs6, 16(r3)
965 ; CHECK-P9-NEXT: xxswapd vs6, vs6
1042 ; CHECK-BE-NEXT: lxv vs6, 96(r3)
1051 ; CHECK-BE-NEXT: xxswapd vs6, vs6
H A Dvec_conv_i64_to_fp32_elts.ll202 ; CHECK-P8-NEXT: xvcvuxdsp vs6, v4
211 ; CHECK-P8-NEXT: xxsldwi v6, vs6, vs6, 3
494 ; CHECK-P8-NEXT: xvcvsxdsp vs6, v4
503 ; CHECK-P8-NEXT: xxsldwi v6, vs6, vs6, 3
H A Dvec_conv_fp32_to_i16_elts.ll179 ; CHECK-P8-NEXT: xxsldwi vs6, v3, v3, 3
185 ; CHECK-P8-NEXT: xscvspdpn f6, vs6
345 ; CHECK-P8-NEXT: xxsldwi vs6, v2, v2, 3
351 ; CHECK-P8-NEXT: xscvspdpn f6, vs6
381 ; CHECK-P8-NEXT: xxsldwi vs6, v4, v4, 1
396 ; CHECK-P8-NEXT: xscvspdpn f6, vs6
811 ; CHECK-P8-NEXT: xxsldwi vs6, v3, v3, 3
817 ; CHECK-P8-NEXT: xscvspdpn f6, vs6
977 ; CHECK-P8-NEXT: xxsldwi vs6, v2, v2, 3
983 ; CHECK-P8-NEXT: xscvspdpn f6, vs6
[all …]
H A Dvec_conv_fp64_to_i16_elts.ll338 ; CHECK-P8-NEXT: xxswapd vs6, vs10
423 ; CHECK-P9-NEXT: xxmrglw vs6, v3, v2
437 ; CHECK-P9-NEXT: xxmrgld vs4, vs4, vs6
510 ; CHECK-BE-NEXT: xxmrghw vs6, v4, v3
524 ; CHECK-BE-NEXT: xxmrghd vs4, vs4, vs6
885 ; CHECK-P8-NEXT: xxswapd vs6, vs10
970 ; CHECK-P9-NEXT: xxmrglw vs6, v3, v2
984 ; CHECK-P9-NEXT: xxmrgld vs4, vs4, vs6
1057 ; CHECK-BE-NEXT: xxmrghw vs6, v4, v3
1071 ; CHECK-BE-NEXT: xxmrghd vs4, vs4, vs6
H A Dvec-trunc2.ll52 ; CHECK-BE-NEXT: lxvw4x vs6, 0, r3
62 ; CHECK-BE-NEXT: xxmrghw vs3, vs7, vs6
H A Dvector-reduce-fmin.ll1061 ; PWR9LE-NEXT: xvmindp vs6, v2, v10
1068 ; PWR9LE-NEXT: xvmindp vs1, vs6, vs1
1088 ; PWR9BE-NEXT: xvmindp vs6, v2, v10
1095 ; PWR9BE-NEXT: xvmindp vs1, vs6, vs1
1112 ; PWR10LE-NEXT: xvmindp vs6, v2, v10
1121 ; PWR10LE-NEXT: xvmindp vs1, vs6, vs1
1139 ; PWR10BE-NEXT: xvmindp vs6, v2, v10
1148 ; PWR10BE-NEXT: xvmindp vs1, vs6, vs1
H A Dvector-reduce-fmax.ll1061 ; PWR9LE-NEXT: xvmaxdp vs6, v2, v10
1068 ; PWR9LE-NEXT: xvmaxdp vs1, vs6, vs1
1088 ; PWR9BE-NEXT: xvmaxdp vs6, v2, v10
1095 ; PWR9BE-NEXT: xvmaxdp vs1, vs6, vs1
1112 ; PWR10LE-NEXT: xvmaxdp vs6, v2, v10
1121 ; PWR10LE-NEXT: xvmaxdp vs1, vs6, vs1
1139 ; PWR10BE-NEXT: xvmaxdp vs6, v2, v10
1148 ; PWR10BE-NEXT: xvmaxdp vs1, vs6, vs1
H A Dppc64-acc-regalloc.ll58 ; CHECK-NEXT: xxlor vs6, v6, v6
145 ; TRACKLIVE-NEXT: xvmuldp vs6, vs0, v2
152 ; TRACKLIVE-NEXT: xvmaddadp vs6, v2, v2
H A Dvec_conv_fp32_to_i8_elts.ll188 ; CHECK-P8-NEXT: xxsldwi vs6, v3, v3, 3
194 ; CHECK-P8-NEXT: xscvspdpn f6, vs6
400 ; CHECK-P8-NEXT: xxsldwi vs6, v7, v7, 1
405 ; CHECK-P8-NEXT: xscvspdpn f6, vs6
828 ; CHECK-P8-NEXT: xxsldwi vs6, v3, v3, 3
834 ; CHECK-P8-NEXT: xscvspdpn f6, vs6
1040 ; CHECK-P8-NEXT: xxsldwi vs6, v7, v7, 1
1045 ; CHECK-P8-NEXT: xscvspdpn f6, vs6
H A Dspill-vec-pair.ll158 …tail call void asm sideeffect "nop", "~{memory},~{vs0},~{vs1},~{vs2},~{vs3},~{vs4},~{vs5},~{vs6},~…
/llvm-project-15.0.7/lldb/source/Plugins/Process/Utility/
H A DRegisterInfos_ppc64le.h212 DEFINE_VSX(vs6, LLDB_INVALID_REGNUM), \
397 uint32_t vs6[4]; member