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Searched refs:vs5 (Results 1 – 19 of 19) sorted by relevance

/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A Dvec_conv_fp32_to_i64_elts.ll196 ; CHECK-P8-NEXT: xvcvspdp vs5, vs5
242 ; CHECK-P9-NEXT: xxmrghw vs5, vs5, vs5
250 ; CHECK-P9-NEXT: xvcvspdp vs5, vs5
258 ; CHECK-P9-NEXT: xvcvdpuxds vs5, vs5
282 ; CHECK-BE-NEXT: xxmrglw vs5, vs5, vs5
290 ; CHECK-BE-NEXT: xvcvspdp vs5, vs5
501 ; CHECK-P8-NEXT: xvcvspdp vs5, vs5
547 ; CHECK-P9-NEXT: xxmrghw vs5, vs5, vs5
555 ; CHECK-P9-NEXT: xvcvspdp vs5, vs5
587 ; CHECK-BE-NEXT: xxmrglw vs5, vs5, vs5
[all …]
H A Dvec_conv_i32_to_fp64_elts.ll189 ; CHECK-P8-NEXT: xxswapd vs1, vs5
206 ; CHECK-P9-NEXT: lxv vs5, 32(r4)
218 ; CHECK-P9-NEXT: xxmrglw v2, vs5, vs5
220 ; CHECK-P9-NEXT: xxmrghw v2, vs5, vs5
238 ; CHECK-BE-NEXT: lxv vs5, 32(r4)
250 ; CHECK-BE-NEXT: xxmrghw v2, vs5, vs5
252 ; CHECK-BE-NEXT: xxmrglw v2, vs5, vs5
478 ; CHECK-P9-NEXT: xxmrglw v2, vs5, vs5
480 ; CHECK-P9-NEXT: xxmrghw v2, vs5, vs5
510 ; CHECK-BE-NEXT: xxmrghw v2, vs5, vs5
[all …]
H A Dvec_conv_fp_to_i_8byte_elts.ll151 ; CHECK-P8-NEXT: xvcvdpuxds vs5, vs5
172 ; CHECK-P9-NEXT: lxv vs5, 32(r4)
177 ; CHECK-P9-NEXT: xvcvdpuxds vs5, vs5
187 ; CHECK-P9-NEXT: stxv vs5, 32(r3)
200 ; CHECK-BE-NEXT: lxv vs5, 32(r4)
205 ; CHECK-BE-NEXT: xvcvdpuxds vs5, vs5
215 ; CHECK-BE-NEXT: stxv vs5, 32(r3)
365 ; CHECK-P8-NEXT: xvcvdpsxds vs5, vs5
386 ; CHECK-P9-NEXT: lxv vs5, 32(r4)
391 ; CHECK-P9-NEXT: xvcvdpsxds vs5, vs5
[all …]
H A Dvector-reduce-fadd.ll1716 ; PWR9LE-NEXT: xxswapd vs5, v3
1723 ; PWR9LE-NEXT: xxswapd vs5, v4
1726 ; PWR9LE-NEXT: xxswapd vs5, v5
2497 ; PWR9BE-NEXT: xxswapd vs5, vs5
2735 ; PWR10BE-NEXT: xxswapd vs5, vs5
2983 ; PWR9BE-NEXT: xxswapd vs5, vs5
3223 ; PWR10BE-NEXT: xxswapd vs5, vs5
3278 ; PWR9LE-NEXT: xvadddp vs5, v9, vs5
3337 ; PWR9BE-NEXT: xvadddp vs5, v9, vs5
3384 ; PWR10LE-NEXT: xvadddp vs5, v9, vs5
[all …]
H A Dvec_conv_i_to_fp_8byte_elts.ll143 ; CHECK-P8-NEXT: lxvd2x vs5, r4, r10
151 ; CHECK-P8-NEXT: xvcvuxddp vs5, vs5
179 ; CHECK-P9-NEXT: xvcvuxddp vs5, v4
184 ; CHECK-P9-NEXT: stxv vs5, 80(r3)
207 ; CHECK-BE-NEXT: xvcvuxddp vs5, v4
212 ; CHECK-BE-NEXT: stxv vs5, 80(r3)
365 ; CHECK-P8-NEXT: xvcvsxddp vs5, vs5
393 ; CHECK-P9-NEXT: xvcvsxddp vs5, v4
398 ; CHECK-P9-NEXT: stxv vs5, 80(r3)
421 ; CHECK-BE-NEXT: xvcvsxddp vs5, v4
[all …]
H A Dvec_conv_fp64_to_i32_elts.ll172 ; CHECK-P8-NEXT: lxvd2x vs5, r4, r7
180 ; CHECK-P8-NEXT: xxmrghd vs3, vs5, vs6
182 ; CHECK-P8-NEXT: xxmrgld vs0, vs5, vs6
207 ; CHECK-P9-NEXT: lxv vs5, 48(r4)
210 ; CHECK-P9-NEXT: xxmrgld vs7, vs5, vs4
211 ; CHECK-P9-NEXT: xxmrghd vs4, vs5, vs4
243 ; CHECK-BE-NEXT: lxv vs5, 32(r4)
246 ; CHECK-BE-NEXT: xxmrgld vs7, vs5, vs4
440 ; CHECK-P8-NEXT: lxvd2x vs5, r4, r7
475 ; CHECK-P9-NEXT: lxv vs5, 48(r4)
[all …]
H A Dvec_conv_i16_to_fp64_elts.ll262 ; CHECK-P8-NEXT: xvcvuxddp vs5, v2
270 ; CHECK-P8-NEXT: xxswapd vs5, vs5
318 ; CHECK-P9-NEXT: xvcvuxddp vs5, v3
325 ; CHECK-P9-NEXT: stxv vs5, 80(r3)
361 ; CHECK-BE-NEXT: xvcvuxddp vs5, v3
368 ; CHECK-BE-NEXT: stxv vs5, 80(r3)
681 ; CHECK-P8-NEXT: xvcvsxddp vs5, v2
691 ; CHECK-P8-NEXT: xxswapd vs5, vs5
741 ; CHECK-P9-NEXT: xvcvsxddp vs5, v2
747 ; CHECK-P9-NEXT: stxv vs5, 80(r3)
[all …]
H A Dvec_conv_fp64_to_i8_elts.ll315 ; CHECK-P8-NEXT: lxvd2x vs5, r3, r4
329 ; CHECK-P8-NEXT: xxswapd vs5, vs5
404 ; CHECK-P9-NEXT: lxv vs5, 32(r3)
418 ; CHECK-P9-NEXT: xxswapd vs5, vs5
486 ; CHECK-BE-NEXT: lxv vs5, 80(r3)
504 ; CHECK-BE-NEXT: xxswapd vs5, vs5
884 ; CHECK-P8-NEXT: xxswapd vs5, vs5
959 ; CHECK-P9-NEXT: lxv vs5, 32(r3)
973 ; CHECK-P9-NEXT: xxswapd vs5, vs5
1041 ; CHECK-BE-NEXT: lxv vs5, 80(r3)
[all …]
H A Dvec_conv_i8_to_fp64_elts.ll277 ; CHECK-P8-NEXT: xvcvuxddp vs5, v2
287 ; CHECK-P8-NEXT: xxswapd vs5, vs5
342 ; CHECK-P9-NEXT: xvcvuxddp vs5, v3
347 ; CHECK-P9-NEXT: stxv vs5, 80(r3)
395 ; CHECK-BE-NEXT: xvcvuxddp vs5, v3
400 ; CHECK-BE-NEXT: stxv vs5, 80(r3)
729 ; CHECK-P8-NEXT: xvcvsxddp vs5, v0
740 ; CHECK-P8-NEXT: xxswapd vs5, vs5
799 ; CHECK-P9-NEXT: xvcvsxddp vs5, v3
804 ; CHECK-P9-NEXT: stxv vs5, 80(r3)
[all …]
H A Dmma-intrinsics.ll304 ; CHECK-NEXT: stxv vs5, 32(r3)
321 ; CHECK-BE-NEXT: stxv vs5, 16(r3)
352 ; CHECK-NEXT: stxv vs5, 32(r3)
369 ; CHECK-BE-NEXT: stxv vs5, 16(r3)
427 ; CHECK-NEXT: stxv vs5, 96(r8)
475 ; CHECK-BE-NEXT: stxv vs5, 80(r8)
563 ; CHECK-NEXT: stxv vs5, 64(r1)
596 ; CHECK-BE-NEXT: stxv vs5, 128(r1)
H A Dvec_conv_i64_to_fp32_elts.ll201 ; CHECK-P8-NEXT: xvcvuxdsp vs5, v3
210 ; CHECK-P8-NEXT: xxsldwi v1, vs5, vs5, 3
493 ; CHECK-P8-NEXT: xvcvsxdsp vs5, v3
502 ; CHECK-P8-NEXT: xxsldwi v1, vs5, vs5, 3
H A Dvec-trunc2.ll50 ; CHECK-BE-NEXT: lxvw4x vs5, 0, r3
58 ; CHECK-BE-NEXT: xxmrghw vs2, vs5, vs4
H A Dvector-reduce-fmin.ll1060 ; PWR9LE-NEXT: xvmindp vs5, v5, v13
1069 ; PWR9LE-NEXT: xvmindp vs2, vs5, vs2
1087 ; PWR9BE-NEXT: xvmindp vs5, v5, v13
1096 ; PWR9BE-NEXT: xvmindp vs2, vs5, vs2
1111 ; PWR10LE-NEXT: xvmindp vs5, v5, v13
1122 ; PWR10LE-NEXT: xvmindp vs2, vs5, vs2
1138 ; PWR10BE-NEXT: xvmindp vs5, v5, v13
1149 ; PWR10BE-NEXT: xvmindp vs2, vs5, vs2
H A Dvector-reduce-fmax.ll1060 ; PWR9LE-NEXT: xvmaxdp vs5, v5, v13
1069 ; PWR9LE-NEXT: xvmaxdp vs2, vs5, vs2
1087 ; PWR9BE-NEXT: xvmaxdp vs5, v5, v13
1096 ; PWR9BE-NEXT: xvmaxdp vs2, vs5, vs2
1111 ; PWR10LE-NEXT: xvmaxdp vs5, v5, v13
1122 ; PWR10LE-NEXT: xvmaxdp vs2, vs5, vs2
1138 ; PWR10BE-NEXT: xvmaxdp vs5, v5, v13
1149 ; PWR10BE-NEXT: xvmaxdp vs2, vs5, vs2
H A Dvec_conv_fp32_to_i16_elts.ll443 ; CHECK-P9-NEXT: xxsldwi vs5, vs0, vs0, 3
460 ; CHECK-P9-NEXT: xscvspdpn f3, vs5
546 ; CHECK-BE-NEXT: xxsldwi vs5, vs0, vs0, 3
563 ; CHECK-BE-NEXT: xscvspdpn f3, vs5
1075 ; CHECK-P9-NEXT: xxsldwi vs5, vs0, vs0, 3
1092 ; CHECK-P9-NEXT: xscvspdpn f3, vs5
1178 ; CHECK-BE-NEXT: xxsldwi vs5, vs0, vs0, 3
1195 ; CHECK-BE-NEXT: xscvspdpn f3, vs5
H A Dvec_conv_fp64_to_i16_elts.ll299 ; CHECK-P8-NEXT: lxvd2x vs5, r4, r6
314 ; CHECK-P8-NEXT: xxswapd vs5, vs5
846 ; CHECK-P8-NEXT: lxvd2x vs5, r4, r6
861 ; CHECK-P8-NEXT: xxswapd vs5, vs5
H A Dppc64-acc-regalloc.ll51 ; CHECK-NEXT: xvmuldp vs5, v14, v2
157 ; TRACKLIVE-NEXT: xvmuldp vs5, v6, v2
H A Dspill-vec-pair.ll158 …tail call void asm sideeffect "nop", "~{memory},~{vs0},~{vs1},~{vs2},~{vs3},~{vs4},~{vs5},~{vs6},~…
/llvm-project-15.0.7/lldb/source/Plugins/Process/Utility/
H A DRegisterInfos_ppc64le.h211 DEFINE_VSX(vs5, LLDB_INVALID_REGNUM), \
396 uint32_t vs5[4]; member