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/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A Dvec_conv_fp64_to_i32_elts.ll102 ; CHECK-P8-NEXT: xvcvdpuxws v2, vs4
120 ; CHECK-P9-NEXT: xvcvdpuxws v2, vs4
140 ; CHECK-BE-NEXT: xvcvdpuxws v2, vs4
206 ; CHECK-P9-NEXT: lxv vs4, 32(r4)
211 ; CHECK-P9-NEXT: xxmrghd vs4, vs5, vs4
242 ; CHECK-BE-NEXT: lxv vs4, 48(r4)
247 ; CHECK-BE-NEXT: xxmrghd vs4, vs5, vs4
474 ; CHECK-P9-NEXT: lxv vs4, 32(r4)
479 ; CHECK-P9-NEXT: xxmrghd vs4, vs5, vs4
510 ; CHECK-BE-NEXT: lxv vs4, 48(r4)
[all …]
H A Dvec_conv_i32_to_fp64_elts.ll188 ; CHECK-P8-NEXT: xxswapd vs4, vs4
207 ; CHECK-P9-NEXT: lxv vs4, 48(r4)
224 ; CHECK-P9-NEXT: xxmrglw v2, vs4, vs4
226 ; CHECK-P9-NEXT: xxmrghw v2, vs4, vs4
256 ; CHECK-BE-NEXT: xxmrghw v2, vs4, vs4
258 ; CHECK-BE-NEXT: xxmrglw v2, vs4, vs4
448 ; CHECK-P8-NEXT: xxswapd vs4, vs4
484 ; CHECK-P9-NEXT: xxmrglw v2, vs4, vs4
486 ; CHECK-P9-NEXT: xxmrghw v2, vs4, vs4
516 ; CHECK-BE-NEXT: xxmrghw v2, vs4, vs4
[all …]
H A Dvec_conv_fp32_to_i64_elts.ll200 ; CHECK-P8-NEXT: xvcvspdp vs4, vs4
213 ; CHECK-P8-NEXT: xxswapd vs4, v2
247 ; CHECK-P9-NEXT: xvcvspdp vs4, vs4
255 ; CHECK-P9-NEXT: xvcvdpuxds vs4, vs4
287 ; CHECK-BE-NEXT: xvcvspdp vs4, vs4
295 ; CHECK-BE-NEXT: xvcvdpuxds vs4, vs4
505 ; CHECK-P8-NEXT: xvcvspdp vs4, vs4
552 ; CHECK-P9-NEXT: xvcvspdp vs4, vs4
560 ; CHECK-P9-NEXT: xvcvdpuxds vs4, vs4
592 ; CHECK-BE-NEXT: xvcvspdp vs4, vs4
[all …]
H A Dvec_conv_fp_to_i_8byte_elts.ll150 ; CHECK-P8-NEXT: xvcvdpuxds vs4, vs4
171 ; CHECK-P9-NEXT: lxv vs4, 48(r4)
178 ; CHECK-P9-NEXT: xvcvdpuxds vs4, vs4
186 ; CHECK-P9-NEXT: stxv vs4, 48(r3)
199 ; CHECK-BE-NEXT: lxv vs4, 48(r4)
206 ; CHECK-BE-NEXT: xvcvdpuxds vs4, vs4
214 ; CHECK-BE-NEXT: stxv vs4, 48(r3)
364 ; CHECK-P8-NEXT: xvcvdpsxds vs4, vs4
385 ; CHECK-P9-NEXT: lxv vs4, 48(r4)
392 ; CHECK-P9-NEXT: xvcvdpsxds vs4, vs4
[all …]
H A Dvec_conv_i_to_fp_8byte_elts.ll142 ; CHECK-P8-NEXT: lxvd2x vs4, r4, r9
150 ; CHECK-P8-NEXT: xvcvuxddp vs4, vs4
170 ; CHECK-P9-NEXT: xvcvuxddp vs4, v5
185 ; CHECK-P9-NEXT: stxv vs4, 64(r3)
198 ; CHECK-BE-NEXT: xvcvuxddp vs4, v5
213 ; CHECK-BE-NEXT: stxv vs4, 64(r3)
364 ; CHECK-P8-NEXT: xvcvsxddp vs4, vs4
384 ; CHECK-P9-NEXT: xvcvsxddp vs4, v5
399 ; CHECK-P9-NEXT: stxv vs4, 64(r3)
412 ; CHECK-BE-NEXT: xvcvsxddp vs4, v5
[all …]
H A Dmma-phi-accs.ll29 ; CHECK-NEXT: lxv vs4, 0(r4)
31 ; CHECK-NEXT: xvf64gerpp acc0, vsp34, vs4
56 ; CHECK-BE-NEXT: lxv vs4, 0(r4)
58 ; CHECK-BE-NEXT: xvf64gerpp acc0, vsp34, vs4
114 ; CHECK-NEXT: lxv vs4, 32(r4)
115 ; CHECK-NEXT: xvf64ger acc0, vsp34, vs4
125 ; CHECK-NEXT: lxv vs4, 0(r4)
127 ; CHECK-NEXT: xvf64gerpp acc0, vsp34, vs4
142 ; CHECK-BE-NEXT: lxv vs4, 32(r4)
143 ; CHECK-BE-NEXT: xvf64ger acc0, vsp34, vs4
[all …]
H A Dvec_conv_fp64_to_i16_elts.ll400 ; CHECK-P9-NEXT: lxv vs4, 48(r4)
409 ; CHECK-P9-NEXT: xxswapd vs4, vs4
437 ; CHECK-P9-NEXT: xxmrgld vs4, vs4, vs6
442 ; CHECK-P9-NEXT: stxv vs4, 0(r3)
487 ; CHECK-BE-NEXT: lxv vs4, 0(r4)
496 ; CHECK-BE-NEXT: xxswapd vs4, vs4
524 ; CHECK-BE-NEXT: xxmrghd vs4, vs4, vs6
956 ; CHECK-P9-NEXT: xxswapd vs4, vs4
984 ; CHECK-P9-NEXT: xxmrgld vs4, vs4, vs6
1043 ; CHECK-BE-NEXT: xxswapd vs4, vs4
[all …]
H A Dvector-reduce-fmin.ll952 ; PWR9LE-NEXT: xvmindp vs4, v5, v13
959 ; PWR9LE-NEXT: xvmindp vs3, vs4, vs3
960 ; PWR9LE-NEXT: xvmindp vs4, v3, v11
961 ; PWR9LE-NEXT: xvmindp vs2, vs4, vs2
977 ; PWR9BE-NEXT: xvmindp vs4, v5, v13
984 ; PWR9BE-NEXT: xvmindp vs3, vs4, vs3
985 ; PWR9BE-NEXT: xvmindp vs4, v3, v11
986 ; PWR9BE-NEXT: xvmindp vs2, vs4, vs2
1002 ; PWR10LE-NEXT: xvmindp vs4, v5, v13
1059 ; PWR9LE-NEXT: xvmindp vs4, v3, v11
[all …]
H A Dvector-reduce-fmax.ll952 ; PWR9LE-NEXT: xvmaxdp vs4, v5, v13
959 ; PWR9LE-NEXT: xvmaxdp vs3, vs4, vs3
960 ; PWR9LE-NEXT: xvmaxdp vs4, v3, v11
961 ; PWR9LE-NEXT: xvmaxdp vs2, vs4, vs2
977 ; PWR9BE-NEXT: xvmaxdp vs4, v5, v13
984 ; PWR9BE-NEXT: xvmaxdp vs3, vs4, vs3
985 ; PWR9BE-NEXT: xvmaxdp vs4, v3, v11
986 ; PWR9BE-NEXT: xvmaxdp vs2, vs4, vs2
1002 ; PWR10LE-NEXT: xvmaxdp vs4, v5, v13
1059 ; PWR9LE-NEXT: xvmaxdp vs4, v3, v11
[all …]
H A Dvector-reduce-fadd.ll2037 ; PWR9BE-NEXT: xxswapd vs4, vs4
2149 ; PWR10BE-NEXT: xxswapd vs4, vs4
2500 ; PWR9BE-NEXT: xxswapd vs4, vs4
2738 ; PWR10BE-NEXT: xxswapd vs4, vs4
2986 ; PWR9BE-NEXT: xxswapd vs4, vs4
3226 ; PWR10BE-NEXT: xxswapd vs4, vs4
3279 ; PWR9LE-NEXT: xvadddp vs4, v11, vs4
3291 ; PWR9LE-NEXT: xvadddp vs4, vs5, vs4
3338 ; PWR9BE-NEXT: xvadddp vs4, v11, vs4
3350 ; PWR9BE-NEXT: xvadddp vs4, vs5, vs4
[all …]
H A Dvec_conv_fp32_to_i8_elts.ll192 ; CHECK-P8-NEXT: xscvspdpn f4, vs4
364 ; CHECK-P8-NEXT: xxswapd v7, vs4
390 ; CHECK-P8-NEXT: xscvspdpn f7, vs4
404 ; CHECK-P8-NEXT: xscvspdpn f4, vs4
453 ; CHECK-P9-NEXT: xscvspdpn f4, vs4
456 ; CHECK-P9-NEXT: xxswapd vs4, vs3
458 ; CHECK-P9-NEXT: xscvspdpn f4, vs4
555 ; CHECK-BE-NEXT: xscvspdpn f4, vs4
558 ; CHECK-BE-NEXT: xxswapd vs4, vs3
1004 ; CHECK-P8-NEXT: xxswapd v7, vs4
[all …]
H A Dvec_conv_i16_to_fp64_elts.ll239 ; CHECK-P8-NEXT: lxvd2x vs4, 0, r4
247 ; CHECK-P8-NEXT: xxswapd v1, vs4
258 ; CHECK-P8-NEXT: xvcvuxddp vs4, v9
266 ; CHECK-P8-NEXT: xxswapd vs4, vs4
316 ; CHECK-P9-NEXT: xvcvuxddp vs4, v3
324 ; CHECK-P9-NEXT: stxv vs4, 64(r3)
359 ; CHECK-BE-NEXT: xvcvuxddp vs4, v3
367 ; CHECK-BE-NEXT: stxv vs4, 64(r3)
645 ; CHECK-P8-NEXT: xxswapd v0, vs4
689 ; CHECK-P8-NEXT: xxswapd vs4, vs4
[all …]
H A Dvec_conv_fp64_to_i8_elts.ll403 ; CHECK-P9-NEXT: lxv vs4, 48(r3)
427 ; CHECK-P9-NEXT: xxswapd vs4, vs4
441 ; CHECK-P9-NEXT: xxmrglw vs4, v3, v2
473 ; CHECK-P9-NEXT: xxmrgld v2, vs0, vs4
485 ; CHECK-BE-NEXT: lxv vs4, 64(r3)
513 ; CHECK-BE-NEXT: xxswapd vs4, vs4
527 ; CHECK-BE-NEXT: xxmrghw vs4, v4, v3
958 ; CHECK-P9-NEXT: lxv vs4, 48(r3)
982 ; CHECK-P9-NEXT: xxswapd vs4, vs4
1040 ; CHECK-BE-NEXT: lxv vs4, 64(r3)
[all …]
H A Dprefer-dqform.ll58 ; CHECK-P9-NEXT: lxv vs4, 0(r3)
62 ; CHECK-P9-NEXT: xvmaddadp vs2, vs4, vs0
113 ; CHECK-P10-NEXT: lxv vs4, 0(r3)
114 ; CHECK-P10-NEXT: xvmaddadp vs2, vs4, vs0
H A Dvec-trunc2.ll25 ; CHECK-NEXT: xxmrghd v3, vs4, vs2
48 ; CHECK-BE-NEXT: lxvw4x vs4, 0, r3
58 ; CHECK-BE-NEXT: xxmrghw vs2, vs5, vs4
89 ; CHECK-NEXT: xxmrghd v3, vs4, vs2
H A Dvec_conv_i64_to_fp32_elts.ll176 ; CHECK-P8-NEXT: lxvd2x vs4, 0, r4
199 ; CHECK-P8-NEXT: xxswapd v5, vs4
200 ; CHECK-P8-NEXT: xvcvuxdsp vs4, v2
208 ; CHECK-P8-NEXT: xxsldwi v0, vs4, vs4, 3
468 ; CHECK-P8-NEXT: lxvd2x vs4, 0, r4
491 ; CHECK-P8-NEXT: xxswapd v5, vs4
492 ; CHECK-P8-NEXT: xvcvsxdsp vs4, v2
500 ; CHECK-P8-NEXT: xxsldwi v0, vs4, vs4, 3
H A Dvec_conv_i8_to_fp64_elts.ll274 ; CHECK-P8-NEXT: xvcvuxddp vs4, v8
282 ; CHECK-P8-NEXT: xxswapd vs4, vs4
336 ; CHECK-P9-NEXT: xvcvuxddp vs4, v3
341 ; CHECK-P9-NEXT: stxv vs4, 64(r3)
389 ; CHECK-BE-NEXT: xvcvuxddp vs4, v3
394 ; CHECK-BE-NEXT: stxv vs4, 64(r3)
726 ; CHECK-P8-NEXT: xvcvsxddp vs4, v6
736 ; CHECK-P8-NEXT: xxswapd vs4, vs4
792 ; CHECK-P9-NEXT: xvcvsxddp vs4, v3
797 ; CHECK-P9-NEXT: stxv vs4, 64(r3)
[all …]
H A Dmma-intrinsics.ll303 ; CHECK-NEXT: stxv vs4, 48(r3)
322 ; CHECK-BE-NEXT: stxv vs4, 0(r3)
351 ; CHECK-NEXT: stxv vs4, 48(r3)
370 ; CHECK-BE-NEXT: stxv vs4, 0(r3)
426 ; CHECK-NEXT: stxv vs4, 112(r8)
476 ; CHECK-BE-NEXT: stxv vs4, 64(r8)
562 ; CHECK-NEXT: stxv vs4, 80(r1)
595 ; CHECK-BE-NEXT: stxv vs4, 112(r1)
H A Dppc64-acc-regalloc.ll56 ; CHECK-NEXT: xxlor vs4, v2, v2
110 ; CHECK-NEXT: stxv vs4, 16(0)
141 ; TRACKLIVE-NEXT: xxlor vs4, v2, v2
202 ; TRACKLIVE-NEXT: stxv vs4, 16(0)
H A Dvec-itofp.ll30 ; CHECK-P8-NEXT: lxvd2x vs4, 0, r5
35 ; CHECK-P8-NEXT: xxswapd v1, vs4
254 ; CHECK-P8-NEXT: lxvd2x vs4, 0, r5
259 ; CHECK-P8-NEXT: xxswapd v0, vs4
H A Dvec_conv_fp32_to_i16_elts.ll177 ; CHECK-P8-NEXT: xxsldwi vs4, v2, v2, 1
183 ; CHECK-P8-NEXT: xscvspdpn f4, vs4
375 ; CHECK-P8-NEXT: xxsldwi vs4, v4, v4, 3
388 ; CHECK-P8-NEXT: xscvspdpn f4, vs4
809 ; CHECK-P8-NEXT: xxsldwi vs4, v2, v2, 1
815 ; CHECK-P8-NEXT: xscvspdpn f4, vs4
1007 ; CHECK-P8-NEXT: xxsldwi vs4, v4, v4, 3
1020 ; CHECK-P8-NEXT: xscvspdpn f4, vs4
/llvm-project-15.0.7/clang/test/Sema/
H A Dext_vector_conversions.c14 short4 vs4; in test() local
18 vs4 += ll; // expected-warning {{implicit conversion loses integer precision}} in test()
H A Dvecshift.c47 vector_short4 vs4; variable
/llvm-project-15.0.7/clang/test/CodeGen/
H A Dvecshift.c45 vector_short4 vs4; variable
/llvm-project-15.0.7/lldb/source/Plugins/Process/Utility/
H A DRegisterInfos_ppc64le.h210 DEFINE_VSX(vs4, LLDB_INVALID_REGNUM), \
395 uint32_t vs4[4]; member

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