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Searched refs:vs2 (Results 1 – 25 of 65) sorted by relevance

123

/llvm-project-15.0.7/clang/test/CodeGen/RISCV/rvv-intrinsics/
H A Dvfwmacc.c179 return vfwmacc_vv_f32mf2(vd, vs1, vs2, vl); in test_vfwmacc_vv_f32mf2()
188 return vfwmacc_vf_f32mf2(vd, vs1, vs2, vl); in test_vfwmacc_vf_f32mf2()
197 return vfwmacc_vv_f32m1(vd, vs1, vs2, vl); in test_vfwmacc_vv_f32m1()
206 return vfwmacc_vf_f32m1(vd, vs1, vs2, vl); in test_vfwmacc_vf_f32m1()
215 return vfwmacc_vv_f32m2(vd, vs1, vs2, vl); in test_vfwmacc_vv_f32m2()
224 return vfwmacc_vf_f32m2(vd, vs1, vs2, vl); in test_vfwmacc_vf_f32m2()
233 return vfwmacc_vv_f32m4(vd, vs1, vs2, vl); in test_vfwmacc_vv_f32m4()
242 return vfwmacc_vf_f32m4(vd, vs1, vs2, vl); in test_vfwmacc_vf_f32m4()
251 return vfwmacc_vv_f32m8(vd, vs1, vs2, vl); in test_vfwmacc_vv_f32m8()
260 return vfwmacc_vf_f32m8(vd, vs1, vs2, vl); in test_vfwmacc_vf_f32m8()
[all …]
H A Dvfwnmacc.c179 return vfwnmacc_vv_f32mf2(vd, vs1, vs2, vl); in test_vfwnmacc_vv_f32mf2()
188 return vfwnmacc_vf_f32mf2(vd, vs1, vs2, vl); in test_vfwnmacc_vf_f32mf2()
197 return vfwnmacc_vv_f32m1(vd, vs1, vs2, vl); in test_vfwnmacc_vv_f32m1()
206 return vfwnmacc_vf_f32m1(vd, vs1, vs2, vl); in test_vfwnmacc_vf_f32m1()
215 return vfwnmacc_vv_f32m2(vd, vs1, vs2, vl); in test_vfwnmacc_vv_f32m2()
224 return vfwnmacc_vf_f32m2(vd, vs1, vs2, vl); in test_vfwnmacc_vf_f32m2()
233 return vfwnmacc_vv_f32m4(vd, vs1, vs2, vl); in test_vfwnmacc_vv_f32m4()
242 return vfwnmacc_vf_f32m4(vd, vs1, vs2, vl); in test_vfwnmacc_vf_f32m4()
251 return vfwnmacc_vv_f32m8(vd, vs1, vs2, vl); in test_vfwnmacc_vv_f32m8()
260 return vfwnmacc_vf_f32m8(vd, vs1, vs2, vl); in test_vfwnmacc_vf_f32m8()
[all …]
H A Dvfwnmsac.c179 return vfwnmsac_vv_f32mf2(vd, vs1, vs2, vl); in test_vfwnmsac_vv_f32mf2()
188 return vfwnmsac_vf_f32mf2(vd, vs1, vs2, vl); in test_vfwnmsac_vf_f32mf2()
197 return vfwnmsac_vv_f32m1(vd, vs1, vs2, vl); in test_vfwnmsac_vv_f32m1()
206 return vfwnmsac_vf_f32m1(vd, vs1, vs2, vl); in test_vfwnmsac_vf_f32m1()
215 return vfwnmsac_vv_f32m2(vd, vs1, vs2, vl); in test_vfwnmsac_vv_f32m2()
224 return vfwnmsac_vf_f32m2(vd, vs1, vs2, vl); in test_vfwnmsac_vf_f32m2()
233 return vfwnmsac_vv_f32m4(vd, vs1, vs2, vl); in test_vfwnmsac_vv_f32m4()
242 return vfwnmsac_vf_f32m4(vd, vs1, vs2, vl); in test_vfwnmsac_vf_f32m4()
251 return vfwnmsac_vv_f32m8(vd, vs1, vs2, vl); in test_vfwnmsac_vv_f32m8()
260 return vfwnmsac_vf_f32m8(vd, vs1, vs2, vl); in test_vfwnmsac_vf_f32m8()
[all …]
H A Dvfwmsac.c179 return vfwmsac_vv_f32mf2(vd, vs1, vs2, vl); in test_vfwmsac_vv_f32mf2()
188 return vfwmsac_vf_f32mf2(vd, vs1, vs2, vl); in test_vfwmsac_vf_f32mf2()
197 return vfwmsac_vv_f32m1(vd, vs1, vs2, vl); in test_vfwmsac_vv_f32m1()
206 return vfwmsac_vf_f32m1(vd, vs1, vs2, vl); in test_vfwmsac_vf_f32m1()
215 return vfwmsac_vv_f32m2(vd, vs1, vs2, vl); in test_vfwmsac_vv_f32m2()
224 return vfwmsac_vf_f32m2(vd, vs1, vs2, vl); in test_vfwmsac_vf_f32m2()
233 return vfwmsac_vv_f32m4(vd, vs1, vs2, vl); in test_vfwmsac_vv_f32m4()
242 return vfwmsac_vf_f32m4(vd, vs1, vs2, vl); in test_vfwmsac_vf_f32m4()
251 return vfwmsac_vv_f32m8(vd, vs1, vs2, vl); in test_vfwmsac_vv_f32m8()
260 return vfwmsac_vf_f32m8(vd, vs1, vs2, vl); in test_vfwmsac_vf_f32m8()
[all …]
H A Dvfnmsub.c385 return vfnmsub_vv_f16mf4(vd, vs1, vs2, vl); in test_vfnmsub_vv_f16mf4()
394 return vfnmsub_vf_f16mf4(vd, rs1, vs2, vl); in test_vfnmsub_vf_f16mf4()
403 return vfnmsub_vv_f16mf2(vd, vs1, vs2, vl); in test_vfnmsub_vv_f16mf2()
421 return vfnmsub_vv_f16m1(vd, vs1, vs2, vl); in test_vfnmsub_vv_f16m1()
430 return vfnmsub_vf_f16m1(vd, rs1, vs2, vl); in test_vfnmsub_vf_f16m1()
439 return vfnmsub_vv_f16m2(vd, vs1, vs2, vl); in test_vfnmsub_vv_f16m2()
448 return vfnmsub_vf_f16m2(vd, rs1, vs2, vl); in test_vfnmsub_vf_f16m2()
457 return vfnmsub_vv_f16m4(vd, vs1, vs2, vl); in test_vfnmsub_vv_f16m4()
466 return vfnmsub_vf_f16m4(vd, rs1, vs2, vl); in test_vfnmsub_vf_f16m4()
475 return vfnmsub_vv_f16m8(vd, vs1, vs2, vl); in test_vfnmsub_vv_f16m8()
[all …]
H A Dvfmacc.c384 return vfmacc_vv_f16mf4(vd, vs1, vs2, vl); in test_vfmacc_vv_f16mf4()
393 return vfmacc_vf_f16mf4(vd, rs1, vs2, vl); in test_vfmacc_vf_f16mf4()
402 return vfmacc_vv_f16mf2(vd, vs1, vs2, vl); in test_vfmacc_vv_f16mf2()
420 return vfmacc_vv_f16m1(vd, vs1, vs2, vl); in test_vfmacc_vv_f16m1()
429 return vfmacc_vf_f16m1(vd, rs1, vs2, vl); in test_vfmacc_vf_f16m1()
438 return vfmacc_vv_f16m2(vd, vs1, vs2, vl); in test_vfmacc_vv_f16m2()
447 return vfmacc_vf_f16m2(vd, rs1, vs2, vl); in test_vfmacc_vf_f16m2()
456 return vfmacc_vv_f16m4(vd, vs1, vs2, vl); in test_vfmacc_vv_f16m4()
465 return vfmacc_vf_f16m4(vd, rs1, vs2, vl); in test_vfmacc_vf_f16m4()
474 return vfmacc_vv_f16m8(vd, vs1, vs2, vl); in test_vfmacc_vv_f16m8()
[all …]
H A Dvfnmsac.c385 return vfnmsac_vv_f16mf4(vd, vs1, vs2, vl); in test_vfnmsac_vv_f16mf4()
394 return vfnmsac_vf_f16mf4(vd, rs1, vs2, vl); in test_vfnmsac_vf_f16mf4()
403 return vfnmsac_vv_f16mf2(vd, vs1, vs2, vl); in test_vfnmsac_vv_f16mf2()
421 return vfnmsac_vv_f16m1(vd, vs1, vs2, vl); in test_vfnmsac_vv_f16m1()
430 return vfnmsac_vf_f16m1(vd, rs1, vs2, vl); in test_vfnmsac_vf_f16m1()
439 return vfnmsac_vv_f16m2(vd, vs1, vs2, vl); in test_vfnmsac_vv_f16m2()
448 return vfnmsac_vf_f16m2(vd, rs1, vs2, vl); in test_vfnmsac_vf_f16m2()
457 return vfnmsac_vv_f16m4(vd, vs1, vs2, vl); in test_vfnmsac_vv_f16m4()
466 return vfnmsac_vf_f16m4(vd, rs1, vs2, vl); in test_vfnmsac_vf_f16m4()
475 return vfnmsac_vv_f16m8(vd, vs1, vs2, vl); in test_vfnmsac_vv_f16m8()
[all …]
H A Dvfmsub.c384 return vfmsub_vv_f16mf4(vd, vs1, vs2, vl); in test_vfmsub_vv_f16mf4()
393 return vfmsub_vf_f16mf4(vd, rs1, vs2, vl); in test_vfmsub_vf_f16mf4()
402 return vfmsub_vv_f16mf2(vd, vs1, vs2, vl); in test_vfmsub_vv_f16mf2()
420 return vfmsub_vv_f16m1(vd, vs1, vs2, vl); in test_vfmsub_vv_f16m1()
429 return vfmsub_vf_f16m1(vd, rs1, vs2, vl); in test_vfmsub_vf_f16m1()
438 return vfmsub_vv_f16m2(vd, vs1, vs2, vl); in test_vfmsub_vv_f16m2()
447 return vfmsub_vf_f16m2(vd, rs1, vs2, vl); in test_vfmsub_vf_f16m2()
456 return vfmsub_vv_f16m4(vd, vs1, vs2, vl); in test_vfmsub_vv_f16m4()
465 return vfmsub_vf_f16m4(vd, rs1, vs2, vl); in test_vfmsub_vf_f16m4()
474 return vfmsub_vv_f16m8(vd, vs1, vs2, vl); in test_vfmsub_vv_f16m8()
[all …]
H A Dvfnmacc.c385 return vfnmacc_vv_f16mf4(vd, vs1, vs2, vl); in test_vfnmacc_vv_f16mf4()
394 return vfnmacc_vf_f16mf4(vd, rs1, vs2, vl); in test_vfnmacc_vf_f16mf4()
403 return vfnmacc_vv_f16mf2(vd, vs1, vs2, vl); in test_vfnmacc_vv_f16mf2()
421 return vfnmacc_vv_f16m1(vd, vs1, vs2, vl); in test_vfnmacc_vv_f16m1()
430 return vfnmacc_vf_f16m1(vd, rs1, vs2, vl); in test_vfnmacc_vf_f16m1()
439 return vfnmacc_vv_f16m2(vd, vs1, vs2, vl); in test_vfnmacc_vv_f16m2()
448 return vfnmacc_vf_f16m2(vd, rs1, vs2, vl); in test_vfnmacc_vf_f16m2()
457 return vfnmacc_vv_f16m4(vd, vs1, vs2, vl); in test_vfnmacc_vv_f16m4()
466 return vfnmacc_vf_f16m4(vd, rs1, vs2, vl); in test_vfnmacc_vf_f16m4()
475 return vfnmacc_vv_f16m8(vd, vs1, vs2, vl); in test_vfnmacc_vv_f16m8()
[all …]
H A Dvfnmadd.c385 return vfnmadd_vv_f16mf4(vd, vs1, vs2, vl); in test_vfnmadd_vv_f16mf4()
394 return vfnmadd_vf_f16mf4(vd, rs1, vs2, vl); in test_vfnmadd_vf_f16mf4()
403 return vfnmadd_vv_f16mf2(vd, vs1, vs2, vl); in test_vfnmadd_vv_f16mf2()
421 return vfnmadd_vv_f16m1(vd, vs1, vs2, vl); in test_vfnmadd_vv_f16m1()
430 return vfnmadd_vf_f16m1(vd, rs1, vs2, vl); in test_vfnmadd_vf_f16m1()
439 return vfnmadd_vv_f16m2(vd, vs1, vs2, vl); in test_vfnmadd_vv_f16m2()
448 return vfnmadd_vf_f16m2(vd, rs1, vs2, vl); in test_vfnmadd_vf_f16m2()
457 return vfnmadd_vv_f16m4(vd, vs1, vs2, vl); in test_vfnmadd_vv_f16m4()
466 return vfnmadd_vf_f16m4(vd, rs1, vs2, vl); in test_vfnmadd_vf_f16m4()
475 return vfnmadd_vv_f16m8(vd, vs1, vs2, vl); in test_vfnmadd_vv_f16m8()
[all …]
H A Dvfmsac.c384 return vfmsac_vv_f16mf4(vd, vs1, vs2, vl); in test_vfmsac_vv_f16mf4()
393 return vfmsac_vf_f16mf4(vd, rs1, vs2, vl); in test_vfmsac_vf_f16mf4()
402 return vfmsac_vv_f16mf2(vd, vs1, vs2, vl); in test_vfmsac_vv_f16mf2()
420 return vfmsac_vv_f16m1(vd, vs1, vs2, vl); in test_vfmsac_vv_f16m1()
429 return vfmsac_vf_f16m1(vd, rs1, vs2, vl); in test_vfmsac_vf_f16m1()
438 return vfmsac_vv_f16m2(vd, vs1, vs2, vl); in test_vfmsac_vv_f16m2()
447 return vfmsac_vf_f16m2(vd, rs1, vs2, vl); in test_vfmsac_vf_f16m2()
456 return vfmsac_vv_f16m4(vd, vs1, vs2, vl); in test_vfmsac_vv_f16m4()
465 return vfmsac_vf_f16m4(vd, rs1, vs2, vl); in test_vfmsac_vf_f16m4()
474 return vfmsac_vv_f16m8(vd, vs1, vs2, vl); in test_vfmsac_vv_f16m8()
[all …]
H A Dvfmadd.c384 return vfmadd_vv_f16mf4(vd, vs1, vs2, vl); in test_vfmadd_vv_f16mf4()
393 return vfmadd_vf_f16mf4(vd, rs1, vs2, vl); in test_vfmadd_vf_f16mf4()
402 return vfmadd_vv_f16mf2(vd, vs1, vs2, vl); in test_vfmadd_vv_f16mf2()
420 return vfmadd_vv_f16m1(vd, vs1, vs2, vl); in test_vfmadd_vv_f16m1()
429 return vfmadd_vf_f16m1(vd, rs1, vs2, vl); in test_vfmadd_vf_f16m1()
438 return vfmadd_vv_f16m2(vd, vs1, vs2, vl); in test_vfmadd_vv_f16m2()
447 return vfmadd_vf_f16m2(vd, rs1, vs2, vl); in test_vfmadd_vf_f16m2()
456 return vfmadd_vv_f16m4(vd, vs1, vs2, vl); in test_vfmadd_vv_f16m4()
465 return vfmadd_vf_f16m4(vd, rs1, vs2, vl); in test_vfmadd_vf_f16m4()
474 return vfmadd_vv_f16m8(vd, vs1, vs2, vl); in test_vfmadd_vv_f16m8()
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A Dvector-reduce-fmin.ll530 ; PWR9LE-NEXT: xvminsp vs2, vs3, vs2
547 ; PWR9BE-NEXT: xvminsp vs2, vs3, vs2
563 ; PWR10LE-NEXT: xvminsp vs2, vs3, vs2
580 ; PWR10BE-NEXT: xvminsp vs2, vs3, vs2
891 ; PWR9LE-NEXT: xvmindp vs2, vs3, vs2
906 ; PWR9BE-NEXT: xvmindp vs2, vs3, vs2
956 ; PWR9LE-NEXT: xvmindp vs2, v7, vs2
961 ; PWR9LE-NEXT: xvmindp vs2, vs4, vs2
981 ; PWR9BE-NEXT: xvmindp vs2, v7, vs2
1064 ; PWR9LE-NEXT: xvmindp vs2, v9, vs2
[all …]
H A Dvector-reduce-fmax.ll530 ; PWR9LE-NEXT: xvmaxsp vs2, vs3, vs2
547 ; PWR9BE-NEXT: xvmaxsp vs2, vs3, vs2
563 ; PWR10LE-NEXT: xvmaxsp vs2, vs3, vs2
580 ; PWR10BE-NEXT: xvmaxsp vs2, vs3, vs2
891 ; PWR9LE-NEXT: xvmaxdp vs2, vs3, vs2
906 ; PWR9BE-NEXT: xvmaxdp vs2, vs3, vs2
956 ; PWR9LE-NEXT: xvmaxdp vs2, v7, vs2
961 ; PWR9LE-NEXT: xvmaxdp vs2, vs4, vs2
981 ; PWR9BE-NEXT: xvmaxdp vs2, v7, vs2
1064 ; PWR9LE-NEXT: xvmaxdp vs2, v9, vs2
[all …]
H A Dvec_conv_fp64_to_i32_elts.ll101 ; CHECK-P8-NEXT: xxmrgld vs2, vs3, vs2
119 ; CHECK-P9-NEXT: xxmrghd vs2, vs3, vs2
139 ; CHECK-BE-NEXT: xxmrghd vs2, vs3, vs2
179 ; CHECK-P8-NEXT: xxmrgld vs2, vs2, vs3
222 ; CHECK-P9-NEXT: xxmrghd vs2, vs3, vs2
258 ; CHECK-BE-NEXT: xxmrghd vs2, vs3, vs2
369 ; CHECK-P8-NEXT: xxmrgld vs2, vs3, vs2
387 ; CHECK-P9-NEXT: xxmrghd vs2, vs3, vs2
407 ; CHECK-BE-NEXT: xxmrghd vs2, vs3, vs2
447 ; CHECK-P8-NEXT: xxmrgld vs2, vs2, vs3
[all …]
H A Dvec_conv_fp32_to_i64_elts.ll103 ; CHECK-P8-NEXT: xvcvspdp vs2, vs2
129 ; CHECK-P9-NEXT: xvcvspdp vs2, vs2
133 ; CHECK-P9-NEXT: xvcvdpuxds vs2, vs2
151 ; CHECK-BE-NEXT: xvcvspdp vs2, vs2
155 ; CHECK-BE-NEXT: xvcvdpuxds vs2, vs2
198 ; CHECK-P8-NEXT: xvcvspdp vs2, vs2
245 ; CHECK-P9-NEXT: xvcvspdp vs2, vs2
285 ; CHECK-BE-NEXT: xvcvspdp vs2, vs2
408 ; CHECK-P8-NEXT: xvcvspdp vs2, vs2
434 ; CHECK-P9-NEXT: xvcvspdp vs2, vs2
[all …]
H A Dvec_conv_fp_to_i_8byte_elts.ll83 ; CHECK-P8-NEXT: xvcvdpuxds vs2, vs2
97 ; CHECK-P9-NEXT: xvcvdpuxds vs2, vs2
113 ; CHECK-BE-NEXT: xvcvdpuxds vs2, vs2
148 ; CHECK-P8-NEXT: xvcvdpuxds vs2, vs2
179 ; CHECK-P9-NEXT: xvcvdpuxds vs2, vs2
207 ; CHECK-BE-NEXT: xvcvdpuxds vs2, vs2
297 ; CHECK-P8-NEXT: xvcvdpsxds vs2, vs2
311 ; CHECK-P9-NEXT: xvcvdpsxds vs2, vs2
327 ; CHECK-BE-NEXT: xvcvdpsxds vs2, vs2
362 ; CHECK-P8-NEXT: xvcvdpsxds vs2, vs2
[all …]
H A Dmma-outer-product.ll21 ; CHECK-NEXT: xxlor vs2, v4, v4
32 ; CHECK-NEXT: stxv vs2, 16(r3)
79 ; CHECK-NEXT: xxlor vs2, v4, v4
90 ; CHECK-NEXT: stxv vs2, 0(r4)
147 ; CHECK-NEXT: stxv vs2, 16(r7)
175 ; CHECK-NEXT: lxv vs2, 16(r3)
181 ; CHECK-NEXT: stxv vs2, 16(r7)
216 ; CHECK-NEXT: stxv vs2, 16(r7)
244 ; CHECK-NEXT: lxv vs2, 16(r3)
313 ; CHECK-NEXT: lxv vs2, 16(r3)
[all …]
H A Dvec_conv_i32_to_fp64_elts.ll98 ; CHECK-P8-NEXT: xxswapd vs2, vs2
184 ; CHECK-P8-NEXT: xxswapd vs2, vs2
212 ; CHECK-P9-NEXT: xxmrglw v2, vs2, vs2
214 ; CHECK-P9-NEXT: xxmrghw v2, vs2, vs2
244 ; CHECK-BE-NEXT: xxmrghw v2, vs2, vs2
246 ; CHECK-BE-NEXT: xxmrglw v2, vs2, vs2
358 ; CHECK-P8-NEXT: xxswapd vs2, vs2
444 ; CHECK-P8-NEXT: xxswapd vs2, vs2
472 ; CHECK-P9-NEXT: xxmrglw v2, vs2, vs2
474 ; CHECK-P9-NEXT: xxmrghw v2, vs2, vs2
[all …]
H A Dvec_conv_i_to_fp_4byte_elts.ll114 ; CHECK-P8-NEXT: xvcvuxwsp vs2, vs2
125 ; CHECK-P9-NEXT: lxv vs2, 16(r4)
128 ; CHECK-P9-NEXT: xvcvuxwsp vs2, vs2
133 ; CHECK-P9-NEXT: stxv vs2, 16(r3)
141 ; CHECK-BE-NEXT: lxv vs2, 16(r4)
144 ; CHECK-BE-NEXT: xvcvuxwsp vs2, vs2
149 ; CHECK-BE-NEXT: stxv vs2, 16(r3)
261 ; CHECK-P8-NEXT: xvcvsxwsp vs2, vs2
272 ; CHECK-P9-NEXT: lxv vs2, 16(r4)
275 ; CHECK-P9-NEXT: xvcvsxwsp vs2, vs2
[all …]
H A Dvec_conv_fp_to_i_4byte_elts.ll114 ; CHECK-P8-NEXT: xvcvspuxws vs2, vs2
125 ; CHECK-P9-NEXT: lxv vs2, 16(r4)
128 ; CHECK-P9-NEXT: xvcvspuxws vs2, vs2
133 ; CHECK-P9-NEXT: stxv vs2, 16(r3)
141 ; CHECK-BE-NEXT: lxv vs2, 16(r4)
144 ; CHECK-BE-NEXT: xvcvspuxws vs2, vs2
149 ; CHECK-BE-NEXT: stxv vs2, 16(r3)
261 ; CHECK-P8-NEXT: xvcvspsxws vs2, vs2
272 ; CHECK-P9-NEXT: lxv vs2, 16(r4)
275 ; CHECK-P9-NEXT: xvcvspsxws vs2, vs2
[all …]
H A Dmma-integer-based-outer-product.ll17 ; CHECK-NEXT: stxv vs2, 16(r7)
28 ; CHECK-BE-NEXT: stxv vs2, 32(r7)
47 ; CHECK-NEXT: stxv vs2, 16(r7)
76 ; CHECK-NEXT: lxv vs2, 16(r3)
82 ; CHECK-NEXT: stxv vs2, 16(r7)
117 ; CHECK-NEXT: lxv vs2, 16(r3)
123 ; CHECK-NEXT: stxv vs2, 16(r7)
158 ; CHECK-NEXT: lxv vs2, 16(r3)
164 ; CHECK-NEXT: stxv vs2, 16(r7)
199 ; CHECK-NEXT: lxv vs2, 16(r3)
[all …]
H A Dbfloat16-outer-product.ll17 ; CHECK-NEXT: stxv vs2, 16(r7)
28 ; CHECK-BE-NEXT: stxv vs2, 32(r7)
48 ; CHECK-NEXT: stxv vs2, 16(r7)
78 ; CHECK-NEXT: lxv vs2, 16(r3)
84 ; CHECK-NEXT: stxv vs2, 16(r7)
121 ; CHECK-NEXT: lxv vs2, 16(r3)
127 ; CHECK-NEXT: stxv vs2, 16(r7)
164 ; CHECK-NEXT: lxv vs2, 16(r3)
207 ; CHECK-NEXT: lxv vs2, 16(r3)
250 ; CHECK-NEXT: lxv vs2, 16(r3)
[all …]
H A Dvec_conv_i_to_fp_8byte_elts.ll79 ; CHECK-P8-NEXT: lxvd2x vs2, r4, r7
83 ; CHECK-P8-NEXT: xvcvuxddp vs2, vs2
98 ; CHECK-P9-NEXT: xvcvuxddp vs2, v3
101 ; CHECK-P9-NEXT: stxv vs2, 32(r3)
114 ; CHECK-BE-NEXT: xvcvuxddp vs2, v3
117 ; CHECK-BE-NEXT: stxv vs2, 32(r3)
148 ; CHECK-P8-NEXT: xvcvuxddp vs2, vs2
187 ; CHECK-P9-NEXT: stxv vs2, 32(r3)
215 ; CHECK-BE-NEXT: stxv vs2, 32(r3)
297 ; CHECK-P8-NEXT: xvcvsxddp vs2, vs2
[all …]
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoV.td278 // op vd, vs2, vs1, vm
292 // op vd, vs1, vs2, vm (reverse the order of vs1 and vs2)
298 // op vd, vs2, vs1
306 // op vd, vs2, rs1, vm
320 // op vd, rs1, vs2, vm (reverse the order of rs1 and vs2)
326 // op vd, vs1, vs2
334 // op vd, vs2, imm, vm
348 // op vd, vs2, imm, vm
1439 let vs2 = 0 in
1447 (ins VR:$vs2), "vmv.x.s", "$vd, $vs2">,
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