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Searched refs:vs12 (Results 1 – 6 of 6) sorted by relevance

/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A Dppc64-acc-regalloc.ll71 ; CHECK-NEXT: xxlor vs12, v10, v10
111 ; CHECK-NEXT: stxv vs12, 48(0)
138 ; TRACKLIVE-NEXT: xxlxor vs12, vs12, vs12
153 ; TRACKLIVE-NEXT: xvmaddadp vs12, vs0, vs12
159 ; TRACKLIVE-NEXT: xxlor vs14, vs12, vs12
160 ; TRACKLIVE-NEXT: xxlor vs12, v2, v2
203 ; TRACKLIVE-NEXT: stxv vs12, 48(0)
H A Dvector-reduce-fadd.ll2290 ; PWR9LE-NEXT: lxv vs12, 336(r1)
2356 ; PWR9LE-NEXT: xxswapd v2, vs12
2408 ; PWR9BE-NEXT: lxv vs12, 352(r1)
2476 ; PWR9BE-NEXT: xxswapd vs12, vs12
2594 ; PWR10LE-NEXT: xxswapd v2, vs12
2714 ; PWR10BE-NEXT: xxswapd vs12, vs12
2771 ; PWR9LE-NEXT: lxv vs12, 352(r1)
2893 ; PWR9BE-NEXT: lxv vs12, 368(r1)
2962 ; PWR9BE-NEXT: xxswapd vs12, vs12
3202 ; PWR10BE-NEXT: xxswapd vs12, vs12
[all …]
H A Dmma-intrinsics.ll413 ; CHECK-NEXT: lxv vs12, 64(r7)
420 ; CHECK-NEXT: xvf32gernp acc0, vs12, vs13
462 ; CHECK-BE-NEXT: lxv vs12, 64(r7)
469 ; CHECK-BE-NEXT: xvf32gernp acc0, vs12, vs13
H A Dspill-vec-pair.ll158 …~{vs2},~{vs3},~{vs4},~{vs5},~{vs6},~{vs7},~{vs8},~{vs9},~{vs10},~{vs11},~{vs12},~{vs13},~{vs14},~{…
/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/
H A Dvrgatherei16-subreg-liveness.ll12 define internal void @foo(<vscale x 1 x i16> %v15, <vscale x 1 x i16> %0, <vscale x 1 x i16> %vs12.…
54 …lvm.vector.insert.nxv8i16.nxv1i16(<vscale x 8 x i16> poison, <vscale x 1 x i16> %vs12.i.i.i, i64 0)
/llvm-project-15.0.7/lldb/source/Plugins/Process/Utility/
H A DRegisterInfos_ppc64le.h218 DEFINE_VSX(vs12, LLDB_INVALID_REGNUM), \
403 uint32_t vs12[4]; member