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Searched refs:vs1 (Results 1 – 25 of 97) sorted by relevance

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/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A Dvector-reduce-fmul.ll20 ; PWR9LE-NEXT: xxswapd vs1, v2
22 ; PWR9LE-NEXT: xscvspdpn f1, vs1
30 ; PWR9BE-NEXT: xscvspdpn f1, vs1
37 ; PWR10LE-NEXT: xxswapd vs1, v2
61 ; PWR9LE-NEXT: xxswapd vs1, v2
1213 ; PWR9BE-NEXT: xvmuldp vs1, vs0, vs1
1230 ; PWR10BE-NEXT: xvmuldp vs1, vs0, vs1
1390 ; PWR9BE-NEXT: xvmuldp vs1, vs0, vs1
1411 ; PWR10BE-NEXT: xvmuldp vs1, vs0, vs1
1675 ; PWR9BE-NEXT: xvmuldp vs1, vs0, vs1
[all …]
H A Dvector-reduce-fmin.ll442 ; PWR9LE-NEXT: xvminsp vs1, vs2, vs1
463 ; PWR9BE-NEXT: xvminsp vs1, vs2, vs1
484 ; PWR10LE-NEXT: xvminsp vs1, vs2, vs1
505 ; PWR10BE-NEXT: xvminsp vs1, vs2, vs1
714 ; PWR9BE-NEXT: xvmindp vs1, vs0, vs1
798 ; PWR9BE-NEXT: xvmindp vs1, vs0, vs1
835 ; PWR9LE-NEXT: xvmindp vs1, vs2, vs1
957 ; PWR9LE-NEXT: xvmindp vs1, v8, vs1
982 ; PWR9BE-NEXT: xvmindp vs1, v8, vs1
1065 ; PWR9LE-NEXT: xvmindp vs1, v6, vs1
[all …]
H A Dvector-reduce-fmax.ll442 ; PWR9LE-NEXT: xvmaxsp vs1, vs2, vs1
463 ; PWR9BE-NEXT: xvmaxsp vs1, vs2, vs1
484 ; PWR10LE-NEXT: xvmaxsp vs1, vs2, vs1
505 ; PWR10BE-NEXT: xvmaxsp vs1, vs2, vs1
714 ; PWR9BE-NEXT: xvmaxdp vs1, vs0, vs1
798 ; PWR9BE-NEXT: xvmaxdp vs1, vs0, vs1
835 ; PWR9LE-NEXT: xvmaxdp vs1, vs2, vs1
957 ; PWR9LE-NEXT: xvmaxdp vs1, v8, vs1
982 ; PWR9BE-NEXT: xvmaxdp vs1, v8, vs1
1065 ; PWR9LE-NEXT: xvmaxdp vs1, v6, vs1
[all …]
H A Dvec_conv_fp32_to_i64_elts.ll51 ; CHECK-P8-NEXT: xvcvspdp vs1, vs1
65 ; CHECK-P9-NEXT: xvcvspdp vs1, vs1
77 ; CHECK-BE-NEXT: xvcvspdp vs1, vs1
126 ; CHECK-P9-NEXT: xxmrghw vs1, vs1, vs1
148 ; CHECK-BE-NEXT: xxmrglw vs1, vs1, vs1
238 ; CHECK-P9-NEXT: xxmrghw vs1, vs1, vs1
278 ; CHECK-BE-NEXT: xxmrglw vs1, vs1, vs1
431 ; CHECK-P9-NEXT: xxmrghw vs1, vs1, vs1
453 ; CHECK-BE-NEXT: xxmrglw vs1, vs1, vs1
543 ; CHECK-P9-NEXT: xxmrghw vs1, vs1, vs1
[all …]
H A Dvector-reduce-fadd.ll1213 ; PWR9BE-NEXT: xvadddp vs1, vs0, vs1
1230 ; PWR10BE-NEXT: xvadddp vs1, vs0, vs1
1390 ; PWR9BE-NEXT: xvadddp vs1, vs0, vs1
1675 ; PWR9BE-NEXT: xvadddp vs1, vs0, vs1
1816 ; PWR9BE-NEXT: xxswapd vs1, vs1
1926 ; PWR10BE-NEXT: xxswapd vs1, vs1
2179 ; PWR9LE-NEXT: xvadddp vs1, v6, vs1
2182 ; PWR9LE-NEXT: xvadddp vs1, vs6, vs1
2206 ; PWR9BE-NEXT: xvadddp vs1, v6, vs1
2509 ; PWR9BE-NEXT: xxswapd vs1, vs1
[all …]
H A Dvec_conv_i_to_fp_4byte_elts.ll69 ; CHECK-P8-NEXT: xvcvuxwsp vs1, vs1
79 ; CHECK-P9-NEXT: xvcvuxwsp vs1, vs1
89 ; CHECK-BE-NEXT: xvcvuxwsp vs1, vs1
113 ; CHECK-P8-NEXT: xvcvuxwsp vs1, vs1
129 ; CHECK-P9-NEXT: xvcvuxwsp vs1, vs1
145 ; CHECK-BE-NEXT: xvcvuxwsp vs1, vs1
216 ; CHECK-P8-NEXT: xvcvsxwsp vs1, vs1
226 ; CHECK-P9-NEXT: xvcvsxwsp vs1, vs1
236 ; CHECK-BE-NEXT: xvcvsxwsp vs1, vs1
260 ; CHECK-P8-NEXT: xvcvsxwsp vs1, vs1
[all …]
H A Dvec_conv_fp_to_i_4byte_elts.ll69 ; CHECK-P8-NEXT: xvcvspuxws vs1, vs1
79 ; CHECK-P9-NEXT: xvcvspuxws vs1, vs1
89 ; CHECK-BE-NEXT: xvcvspuxws vs1, vs1
113 ; CHECK-P8-NEXT: xvcvspuxws vs1, vs1
129 ; CHECK-P9-NEXT: xvcvspuxws vs1, vs1
145 ; CHECK-BE-NEXT: xvcvspuxws vs1, vs1
216 ; CHECK-P8-NEXT: xvcvspsxws vs1, vs1
226 ; CHECK-P9-NEXT: xvcvspsxws vs1, vs1
236 ; CHECK-BE-NEXT: xvcvspsxws vs1, vs1
260 ; CHECK-P8-NEXT: xvcvspsxws vs1, vs1
[all …]
H A Dvec_conv_fp_to_i_8byte_elts.ll38 ; CHECK-P8-NEXT: xvcvdpuxds vs1, vs1
48 ; CHECK-P9-NEXT: xvcvdpuxds vs1, vs1
58 ; CHECK-BE-NEXT: xvcvdpuxds vs1, vs1
82 ; CHECK-P8-NEXT: xvcvdpuxds vs1, vs1
98 ; CHECK-P9-NEXT: xvcvdpuxds vs1, vs1
114 ; CHECK-BE-NEXT: xvcvdpuxds vs1, vs1
147 ; CHECK-P8-NEXT: xvcvdpuxds vs1, vs1
180 ; CHECK-P9-NEXT: xvcvdpuxds vs1, vs1
208 ; CHECK-BE-NEXT: xvcvdpuxds vs1, vs1
252 ; CHECK-P8-NEXT: xvcvdpsxds vs1, vs1
[all …]
H A Dvector-reduce-and.ll57 ; PWR9LE-NEXT: xxspltw vs1, vs0, 2
58 ; PWR9LE-NEXT: xxland v2, vs0, vs1
67 ; PWR9BE-NEXT: xxspltw vs1, vs0, 1
68 ; PWR9BE-NEXT: xxland v2, vs0, vs1
103 ; PWR9LE-NEXT: xxspltw vs1, vs0, 2
125 ; PWR10LE-NEXT: xxspltw vs1, vs1, 2
136 ; PWR10BE-NEXT: xxspltw vs1, vs1, 1
149 ; PWR9LE-NEXT: xxland vs1, v2, v4
162 ; PWR9BE-NEXT: xxland vs1, v2, v4
359 ; PWR10LE-NEXT: xxeval vs1, vs1, v4, v8, 1
[all …]
H A Dvec_conv_i32_to_fp64_elts.ll50 ; CHECK-P8-NEXT: xxswapd vs1, vs1
100 ; CHECK-P8-NEXT: xxswapd vs1, vs1
112 ; CHECK-P9-NEXT: xxmrglw v2, vs1, vs1
114 ; CHECK-P9-NEXT: xxmrghw v2, vs1, vs1
130 ; CHECK-BE-NEXT: xxmrghw v2, vs1, vs1
132 ; CHECK-BE-NEXT: xxmrglw v2, vs1, vs1
183 ; CHECK-P8-NEXT: xxswapd vs1, vs1
310 ; CHECK-P8-NEXT: xxswapd vs1, vs1
360 ; CHECK-P8-NEXT: xxswapd vs1, vs1
372 ; CHECK-P9-NEXT: xxmrglw v2, vs1, vs1
[all …]
H A Dvector-reduce-or.ll57 ; PWR9LE-NEXT: xxspltw vs1, vs0, 2
58 ; PWR9LE-NEXT: xxlor v2, vs0, vs1
67 ; PWR9BE-NEXT: xxspltw vs1, vs0, 1
68 ; PWR9BE-NEXT: xxlor v2, vs0, vs1
78 ; PWR10LE-NEXT: xxlor v2, vs0, vs1
88 ; PWR10BE-NEXT: xxlor v2, vs0, vs1
104 ; PWR9LE-NEXT: xxlor v2, vs0, vs1
115 ; PWR9BE-NEXT: xxlor v2, vs0, vs1
149 ; PWR9LE-NEXT: xxlor vs1, v2, v4
155 ; PWR9LE-NEXT: xxlor v2, vs0, vs1
[all …]
H A Dvector-reduce-xor.ll57 ; PWR9LE-NEXT: xxspltw vs1, vs0, 2
58 ; PWR9LE-NEXT: xxlxor v2, vs0, vs1
67 ; PWR9BE-NEXT: xxspltw vs1, vs0, 1
68 ; PWR9BE-NEXT: xxlxor v2, vs0, vs1
77 ; PWR10LE-NEXT: xxspltw vs1, vs0, 2
103 ; PWR9LE-NEXT: xxspltw vs1, vs0, 2
104 ; PWR9LE-NEXT: xxlxor v2, vs0, vs1
114 ; PWR9BE-NEXT: xxspltw vs1, vs0, 1
115 ; PWR9BE-NEXT: xxlxor v2, vs0, vs1
149 ; PWR9LE-NEXT: xxlxor vs1, v2, v4
[all …]
H A Dreduce_scalarization02.ll15 ; CHECK-NEXT: xxmrglw vs1, vs0, vs0
17 ; CHECK-NEXT: xvcvspdp vs1, vs1
19 ; CHECK-NEXT: stxv vs1, 0(r4)
26 ; CHECK-BE-NEXT: xxmrghw vs1, vs0, vs0
28 ; CHECK-BE-NEXT: xvcvspdp vs1, vs1
30 ; CHECK-BE-NEXT: stxv vs1, 0(r4)
50 ; CHECK-NEXT: xxmrglw vs1, vs0, vs0
52 ; CHECK-NEXT: xvcvspdp vs1, vs1
54 ; CHECK-NEXT: stxv vs1, 0(r4)
63 ; CHECK-BE-NEXT: xvcvspdp vs1, vs1
[all …]
H A Dvec_conv_fp64_to_i32_elts.ll25 ; CHECK-P9-NEXT: xxswapd vs1, v2
50 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r3
52 ; CHECK-P8-NEXT: xxswapd vs1, vs1
64 ; CHECK-P9-NEXT: lxv vs1, 16(r3)
75 ; CHECK-BE-NEXT: lxv vs1, 0(r3)
117 ; CHECK-P9-NEXT: lxv vs1, 48(r4)
137 ; CHECK-BE-NEXT: lxv vs1, 32(r4)
251 ; CHECK-BE-NEXT: lxv vs1, 96(r4)
293 ; CHECK-P9-NEXT: xxswapd vs1, v2
320 ; CHECK-P8-NEXT: xxswapd vs1, vs1
[all …]
H A Dvec_conv_fp32_to_i16_elts.ll233 ; CHECK-P9-NEXT: xxsldwi vs1, vs1, vs1, 1
287 ; CHECK-BE-NEXT: xxsldwi vs1, vs1, vs1, 1
442 ; CHECK-P9-NEXT: xxsldwi vs1, vs1, vs1, 1
519 ; CHECK-P9-NEXT: xxsldwi vs1, vs1, vs1, 1
545 ; CHECK-BE-NEXT: xxsldwi vs1, vs1, vs1, 1
622 ; CHECK-BE-NEXT: xxsldwi vs1, vs1, vs1, 1
865 ; CHECK-P9-NEXT: xxsldwi vs1, vs1, vs1, 1
919 ; CHECK-BE-NEXT: xxsldwi vs1, vs1, vs1, 1
1074 ; CHECK-P9-NEXT: xxsldwi vs1, vs1, vs1, 1
1151 ; CHECK-P9-NEXT: xxsldwi vs1, vs1, vs1, 1
[all …]
/llvm-project-15.0.7/clang/test/CodeGen/RISCV/rvv-intrinsics/
H A Dvfwmacc.c179 return vfwmacc_vv_f32mf2(vd, vs1, vs2, vl); in test_vfwmacc_vv_f32mf2()
188 return vfwmacc_vf_f32mf2(vd, vs1, vs2, vl); in test_vfwmacc_vf_f32mf2()
197 return vfwmacc_vv_f32m1(vd, vs1, vs2, vl); in test_vfwmacc_vv_f32m1()
206 return vfwmacc_vf_f32m1(vd, vs1, vs2, vl); in test_vfwmacc_vf_f32m1()
215 return vfwmacc_vv_f32m2(vd, vs1, vs2, vl); in test_vfwmacc_vv_f32m2()
224 return vfwmacc_vf_f32m2(vd, vs1, vs2, vl); in test_vfwmacc_vf_f32m2()
233 return vfwmacc_vv_f32m4(vd, vs1, vs2, vl); in test_vfwmacc_vv_f32m4()
242 return vfwmacc_vf_f32m4(vd, vs1, vs2, vl); in test_vfwmacc_vf_f32m4()
251 return vfwmacc_vv_f32m8(vd, vs1, vs2, vl); in test_vfwmacc_vv_f32m8()
260 return vfwmacc_vf_f32m8(vd, vs1, vs2, vl); in test_vfwmacc_vf_f32m8()
[all …]
H A Dvfwnmacc.c179 return vfwnmacc_vv_f32mf2(vd, vs1, vs2, vl); in test_vfwnmacc_vv_f32mf2()
188 return vfwnmacc_vf_f32mf2(vd, vs1, vs2, vl); in test_vfwnmacc_vf_f32mf2()
197 return vfwnmacc_vv_f32m1(vd, vs1, vs2, vl); in test_vfwnmacc_vv_f32m1()
206 return vfwnmacc_vf_f32m1(vd, vs1, vs2, vl); in test_vfwnmacc_vf_f32m1()
215 return vfwnmacc_vv_f32m2(vd, vs1, vs2, vl); in test_vfwnmacc_vv_f32m2()
224 return vfwnmacc_vf_f32m2(vd, vs1, vs2, vl); in test_vfwnmacc_vf_f32m2()
233 return vfwnmacc_vv_f32m4(vd, vs1, vs2, vl); in test_vfwnmacc_vv_f32m4()
242 return vfwnmacc_vf_f32m4(vd, vs1, vs2, vl); in test_vfwnmacc_vf_f32m4()
251 return vfwnmacc_vv_f32m8(vd, vs1, vs2, vl); in test_vfwnmacc_vv_f32m8()
260 return vfwnmacc_vf_f32m8(vd, vs1, vs2, vl); in test_vfwnmacc_vf_f32m8()
[all …]
H A Dvfwnmsac.c179 return vfwnmsac_vv_f32mf2(vd, vs1, vs2, vl); in test_vfwnmsac_vv_f32mf2()
188 return vfwnmsac_vf_f32mf2(vd, vs1, vs2, vl); in test_vfwnmsac_vf_f32mf2()
197 return vfwnmsac_vv_f32m1(vd, vs1, vs2, vl); in test_vfwnmsac_vv_f32m1()
206 return vfwnmsac_vf_f32m1(vd, vs1, vs2, vl); in test_vfwnmsac_vf_f32m1()
215 return vfwnmsac_vv_f32m2(vd, vs1, vs2, vl); in test_vfwnmsac_vv_f32m2()
224 return vfwnmsac_vf_f32m2(vd, vs1, vs2, vl); in test_vfwnmsac_vf_f32m2()
233 return vfwnmsac_vv_f32m4(vd, vs1, vs2, vl); in test_vfwnmsac_vv_f32m4()
242 return vfwnmsac_vf_f32m4(vd, vs1, vs2, vl); in test_vfwnmsac_vf_f32m4()
251 return vfwnmsac_vv_f32m8(vd, vs1, vs2, vl); in test_vfwnmsac_vv_f32m8()
260 return vfwnmsac_vf_f32m8(vd, vs1, vs2, vl); in test_vfwnmsac_vf_f32m8()
[all …]
H A Dvfwmsac.c179 return vfwmsac_vv_f32mf2(vd, vs1, vs2, vl); in test_vfwmsac_vv_f32mf2()
188 return vfwmsac_vf_f32mf2(vd, vs1, vs2, vl); in test_vfwmsac_vf_f32mf2()
197 return vfwmsac_vv_f32m1(vd, vs1, vs2, vl); in test_vfwmsac_vv_f32m1()
206 return vfwmsac_vf_f32m1(vd, vs1, vs2, vl); in test_vfwmsac_vf_f32m1()
215 return vfwmsac_vv_f32m2(vd, vs1, vs2, vl); in test_vfwmsac_vv_f32m2()
224 return vfwmsac_vf_f32m2(vd, vs1, vs2, vl); in test_vfwmsac_vf_f32m2()
233 return vfwmsac_vv_f32m4(vd, vs1, vs2, vl); in test_vfwmsac_vv_f32m4()
242 return vfwmsac_vf_f32m4(vd, vs1, vs2, vl); in test_vfwmsac_vf_f32m4()
251 return vfwmsac_vv_f32m8(vd, vs1, vs2, vl); in test_vfwmsac_vv_f32m8()
260 return vfwmsac_vf_f32m8(vd, vs1, vs2, vl); in test_vfwmsac_vf_f32m8()
[all …]
H A Dvfnmsub.c385 return vfnmsub_vv_f16mf4(vd, vs1, vs2, vl); in test_vfnmsub_vv_f16mf4()
403 return vfnmsub_vv_f16mf2(vd, vs1, vs2, vl); in test_vfnmsub_vv_f16mf2()
421 return vfnmsub_vv_f16m1(vd, vs1, vs2, vl); in test_vfnmsub_vv_f16m1()
439 return vfnmsub_vv_f16m2(vd, vs1, vs2, vl); in test_vfnmsub_vv_f16m2()
457 return vfnmsub_vv_f16m4(vd, vs1, vs2, vl); in test_vfnmsub_vv_f16m4()
475 return vfnmsub_vv_f16m8(vd, vs1, vs2, vl); in test_vfnmsub_vv_f16m8()
499 return vfnmsub_vv_f16mf4_m(mask, vd, vs1, vs2, vl); in test_vfnmsub_vv_f16mf4_m()
535 return vfnmsub_vv_f16m1_m(mask, vd, vs1, vs2, vl); in test_vfnmsub_vv_f16m1_m()
553 return vfnmsub_vv_f16m2_m(mask, vd, vs1, vs2, vl); in test_vfnmsub_vv_f16m2_m()
571 return vfnmsub_vv_f16m4_m(mask, vd, vs1, vs2, vl); in test_vfnmsub_vv_f16m4_m()
[all …]
H A Dvfmacc.c384 return vfmacc_vv_f16mf4(vd, vs1, vs2, vl); in test_vfmacc_vv_f16mf4()
402 return vfmacc_vv_f16mf2(vd, vs1, vs2, vl); in test_vfmacc_vv_f16mf2()
420 return vfmacc_vv_f16m1(vd, vs1, vs2, vl); in test_vfmacc_vv_f16m1()
438 return vfmacc_vv_f16m2(vd, vs1, vs2, vl); in test_vfmacc_vv_f16m2()
456 return vfmacc_vv_f16m4(vd, vs1, vs2, vl); in test_vfmacc_vv_f16m4()
474 return vfmacc_vv_f16m8(vd, vs1, vs2, vl); in test_vfmacc_vv_f16m8()
492 return vfmacc_vv_f16mf4_m(mask, vd, vs1, vs2, vl); in test_vfmacc_vv_f16mf4_m()
528 return vfmacc_vv_f16m1_m(mask, vd, vs1, vs2, vl); in test_vfmacc_vv_f16m1_m()
546 return vfmacc_vv_f16m2_m(mask, vd, vs1, vs2, vl); in test_vfmacc_vv_f16m2_m()
564 return vfmacc_vv_f16m4_m(mask, vd, vs1, vs2, vl); in test_vfmacc_vv_f16m4_m()
[all …]
H A Dvfnmsac.c385 return vfnmsac_vv_f16mf4(vd, vs1, vs2, vl); in test_vfnmsac_vv_f16mf4()
403 return vfnmsac_vv_f16mf2(vd, vs1, vs2, vl); in test_vfnmsac_vv_f16mf2()
421 return vfnmsac_vv_f16m1(vd, vs1, vs2, vl); in test_vfnmsac_vv_f16m1()
439 return vfnmsac_vv_f16m2(vd, vs1, vs2, vl); in test_vfnmsac_vv_f16m2()
457 return vfnmsac_vv_f16m4(vd, vs1, vs2, vl); in test_vfnmsac_vv_f16m4()
475 return vfnmsac_vv_f16m8(vd, vs1, vs2, vl); in test_vfnmsac_vv_f16m8()
493 return vfnmsac_vv_f16mf4_m(mask, vd, vs1, vs2, vl); in test_vfnmsac_vv_f16mf4_m()
529 return vfnmsac_vv_f16m1_m(mask, vd, vs1, vs2, vl); in test_vfnmsac_vv_f16m1_m()
547 return vfnmsac_vv_f16m2_m(mask, vd, vs1, vs2, vl); in test_vfnmsac_vv_f16m2_m()
565 return vfnmsac_vv_f16m4_m(mask, vd, vs1, vs2, vl); in test_vfnmsac_vv_f16m4_m()
[all …]
H A Dvfmsub.c384 return vfmsub_vv_f16mf4(vd, vs1, vs2, vl); in test_vfmsub_vv_f16mf4()
402 return vfmsub_vv_f16mf2(vd, vs1, vs2, vl); in test_vfmsub_vv_f16mf2()
420 return vfmsub_vv_f16m1(vd, vs1, vs2, vl); in test_vfmsub_vv_f16m1()
438 return vfmsub_vv_f16m2(vd, vs1, vs2, vl); in test_vfmsub_vv_f16m2()
456 return vfmsub_vv_f16m4(vd, vs1, vs2, vl); in test_vfmsub_vv_f16m4()
474 return vfmsub_vv_f16m8(vd, vs1, vs2, vl); in test_vfmsub_vv_f16m8()
492 return vfmsub_vv_f16mf4_m(mask, vd, vs1, vs2, vl); in test_vfmsub_vv_f16mf4_m()
528 return vfmsub_vv_f16m1_m(mask, vd, vs1, vs2, vl); in test_vfmsub_vv_f16m1_m()
546 return vfmsub_vv_f16m2_m(mask, vd, vs1, vs2, vl); in test_vfmsub_vv_f16m2_m()
564 return vfmsub_vv_f16m4_m(mask, vd, vs1, vs2, vl); in test_vfmsub_vv_f16m4_m()
[all …]
H A Dvfnmacc.c385 return vfnmacc_vv_f16mf4(vd, vs1, vs2, vl); in test_vfnmacc_vv_f16mf4()
403 return vfnmacc_vv_f16mf2(vd, vs1, vs2, vl); in test_vfnmacc_vv_f16mf2()
421 return vfnmacc_vv_f16m1(vd, vs1, vs2, vl); in test_vfnmacc_vv_f16m1()
439 return vfnmacc_vv_f16m2(vd, vs1, vs2, vl); in test_vfnmacc_vv_f16m2()
457 return vfnmacc_vv_f16m4(vd, vs1, vs2, vl); in test_vfnmacc_vv_f16m4()
475 return vfnmacc_vv_f16m8(vd, vs1, vs2, vl); in test_vfnmacc_vv_f16m8()
493 return vfnmacc_vv_f16mf4_m(mask, vd, vs1, vs2, vl); in test_vfnmacc_vv_f16mf4_m()
529 return vfnmacc_vv_f16m1_m(mask, vd, vs1, vs2, vl); in test_vfnmacc_vv_f16m1_m()
547 return vfnmacc_vv_f16m2_m(mask, vd, vs1, vs2, vl); in test_vfnmacc_vv_f16m2_m()
565 return vfnmacc_vv_f16m4_m(mask, vd, vs1, vs2, vl); in test_vfnmacc_vv_f16m4_m()
[all …]
H A Dvfnmadd.c385 return vfnmadd_vv_f16mf4(vd, vs1, vs2, vl); in test_vfnmadd_vv_f16mf4()
403 return vfnmadd_vv_f16mf2(vd, vs1, vs2, vl); in test_vfnmadd_vv_f16mf2()
421 return vfnmadd_vv_f16m1(vd, vs1, vs2, vl); in test_vfnmadd_vv_f16m1()
439 return vfnmadd_vv_f16m2(vd, vs1, vs2, vl); in test_vfnmadd_vv_f16m2()
457 return vfnmadd_vv_f16m4(vd, vs1, vs2, vl); in test_vfnmadd_vv_f16m4()
475 return vfnmadd_vv_f16m8(vd, vs1, vs2, vl); in test_vfnmadd_vv_f16m8()
493 return vfnmadd_vv_f16mf4_m(mask, vd, vs1, vs2, vl); in test_vfnmadd_vv_f16mf4_m()
529 return vfnmadd_vv_f16m1_m(mask, vd, vs1, vs2, vl); in test_vfnmadd_vv_f16m1_m()
547 return vfnmadd_vv_f16m2_m(mask, vd, vs1, vs2, vl); in test_vfnmadd_vv_f16m2_m()
565 return vfnmadd_vv_f16m4_m(mask, vd, vs1, vs2, vl); in test_vfnmadd_vv_f16m4_m()
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