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/llvm-project-15.0.7/libc/AOR_v20.02/string/arm/
H A Dmemcpy.S86 .macro cpy_line_vfp vreg, base
87 vstr \vreg, [dst, #\base]
88 vldr \vreg, [src, #\base]
95 vstr \vreg, [dst, #\base + 32]
96 vldr \vreg, [src, #\base + prefetch_lines * 64 - 32]
105 .macro cpy_tail_vfp vreg, base
106 vstr \vreg, [dst, #\base]
107 vldr \vreg, [src, #\base]
114 vstr \vreg, [dst, #\base + 32]
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dfast-isel-shift-materialize.ll6 ; When materializing the '2' for the shifts below, the second shift kills the vreg
7 ; we materialize in to. However, the first shift was also killing that vreg.
H A Dfast-isel-remat-same-constant.ll7 ; generated by the GEPs. The first add generated killed the vreg for the #6680 constant which shou…
9 ; down. This meant the next use of the vreg for #6680 was after the first which had killed it.
H A Dfast-isel-update-valuemap-for-extract.ll6 ; This test ensures that when fast-isel rewrites uses of the vreg for %tmp29, it also
/llvm-project-15.0.7/llvm/test/CodeGen/MIR/X86/
H A Dmircanon-flags.mir2 # RUN: llc -march=x86-64 -run-pass mir-canonicalizer -mir-vreg-namer-use-stable-hash -verify-machin…
4 # naming collisions with the new vreg renamers naming scheme.
H A Dmir-canon-hash-bb.mir3 # RUN: llc -run-pass mir-namer -mir-vreg-namer-use-stable-hash -x mir -verify-machineinstrs %s -o …
4 # RUN: llc -run-pass mir-canonicalizer -mir-vreg-namer-use-stable-hash -x mir -verify-machineinstr…
H A Dmir-namer-hash-frameindex.mir2 # RUN: llc -mtriple x86_64-linux-gnu -run-pass mir-canonicalizer -mir-vreg-namer-use-stable-hash -v…
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dfast-isel-bitcast-crash.ll4 ; This used to crash due to the bitcast in the entry block reusing the vreg
7 ; was fixed by emitting a reg-reg copy for the bitcast so the vreg type will
H A Dstatepoint-vreg-twoaddr.mir7 ; ModuleID = 'statepoint-vreg-twoaddr.ll'
8 source_filename = "statepoint-vreg-twoaddr.ll"
H A Dearly-ifcvt-crash.ll11 ; on an inline asm instruction is not a vreg def.
H A Dstatepoint-vreg.mir5 ; ModuleID = 'test/CodeGen/X86/statepoint-vreg.ll'
6 source_filename = "test/CodeGen/X86/statepoint-vreg.ll"
/llvm-project-15.0.7/llvm/test/CodeGen/MIR/Generic/
H A DCFPImmMIRCanonHash.mir2 # RUN: llc -run-pass mir-canonicalizer -mir-vreg-namer-use-stable-hash -verify-machineinstrs -o - %…
/llvm-project-15.0.7/llvm/test/CodeGen/MIR/AArch64/
H A Dmir-canon-constant-pool-hash.mir2 # RUN: llc -o - -run-pass mir-canonicalizer -mir-vreg-namer-use-stable-hash -verify-machineinstrs %…
H A Dmir-canon-jump-table.mir2 # RUN: llc -run-pass mir-canonicalizer -mir-vreg-namer-use-stable-hash -verify-machineinstrs -mtrip…
H A Daddrspace-memoperands.mir3 # RUN: llc -mtriple=aarch64-none-linux-gnu -run-pass mir-canonicalizer -mir-vreg-namer-use-stable-h…
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dgreedy-broken-ssa-verifier-error.mir4 # introduces vreg defs when the MIR parser infers SSA.
H A Dconstant-fold-mi-operands.ll95 %vreg = load volatile i64, i64 addrspace(1)* undef
96 %ctpop = call i64 @llvm.ctpop.i64(i64 %vreg)
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/GlobalISel/
H A Dirtranslator-bitcast.ll3 ; Check that we don't invalidate the vreg map.
/llvm-project-15.0.7/llvm/utils/
H A Dupdate_mir_test_checks.py185 for vreg in VREG_RE.finditer(m.group('vregs')):
187 vreg_map[vreg.group(1)] = name
189 vreg.group(1), '[[{}:%[0-9]+]]'.format(name), 1)
/llvm-project-15.0.7/llvm/test/CodeGen/MIR/AMDGPU/
H A Dparse-order-reserved-regs.mir3 # RUN: llc -march=amdgcn -run-pass mir-canonicalizer -mir-vreg-namer-use-stable-hash -verify-machi…
H A Dmircanon-memoperands.mir2 # RUN: llc -march=amdgcn -mcpu=tahiti -run-pass mir-canonicalizer -mir-vreg-namer-use-stable-hash -…
/llvm-project-15.0.7/llvm/test/DebugInfo/MIR/InstrRef/
H A Dphi-coalesce-subreg.mir13 # registers are coalesced across subregisters. Specifically, vreg %2 below is
15 # vreg during coalescing. We should survive this transformation, and emit a
136 ; Verify that vreg 17 is coalesced into a gr32, and not copied any further.
/llvm-project-15.0.7/llvm/test/DebugInfo/MIR/X86/
H A Dmachine-cse.mir6 # They both depend on the COPY of a vreg to %100 in the entry block.
100 ; Capture vreg num for subreg move for later checks; test that the COPY
101 ; of that vreg is optimized out.
/llvm-project-15.0.7/lldb/source/Plugins/Process/Utility/
H A DRegisterInfos_arm64_sve.h308 #define DEFINE_VREG_SVE(vreg, zreg) \ argument
310 #vreg, nullptr, 16, 0, lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, \
311 VREG_KIND(vreg), g_contained_##zreg, g_sve_##vreg##_invalidates, \
/llvm-project-15.0.7/llvm/test/DebugInfo/ARM/
H A Dselectiondag-deadcode.ll16 ; of the vreg holding %agg.result) the dbg_value becomes dangling

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