Home
last modified time | relevance | path

Searched refs:vo (Results 1 – 23 of 23) sorted by relevance

/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dunaligned_load_store_vector.ll12 %vo = bitcast i8* %po to <8 x i8>*
16 store <8 x i8> %v1, <8 x i8>* %vo, align 1
30 %vo = bitcast i8* %po to <4 x i16>*
48 %vo = bitcast i8* %po to <2 x i32>*
66 %vo = bitcast i8* %po to <2 x float>*
84 %vo = bitcast i8* %po to <16 x i8>*
102 %vo = bitcast i8* %po to <8 x i16>*
120 %vo = bitcast i8* %po to <4 x i32>*
138 %vo = bitcast i8* %po to <2 x i64>*
174 %vo = bitcast i8* %po to <8 x i8>*
[all …]
/llvm-project-15.0.7/libcxx/test/std/containers/sequences/vector/vector.cons/
H A Dmove.addressof.compile.pass.cpp24 std::vector<operator_hijacker> vo; in test() local
25 std::vector<operator_hijacker> v(std::move(vo)); in test()
28 std::vector<operator_hijacker> vo; in test() local
29 std::vector<operator_hijacker> v(std::move(vo), std::allocator<operator_hijacker>()); in test()
H A Dassign_copy.addressof.compile.pass.cpp21 std::vector<operator_hijacker> vo; in test() local
23 v = vo; in test()
H A Dassign_move.addressof.compile.pass.cpp21 std::vector<operator_hijacker> vo; in test() local
23 v = std::move(vo); in test()
/llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/
H A Dvec-or-01.ll8 ; CHECK: vo %v24, %v26, %v28
17 ; CHECK: vo %v24, %v26, %v28
26 ; CHECK: vo %v24, %v26, %v28
35 ; CHECK: vo %v24, %v26, %v28
H A Dvec-cmp-06.ll20 ; CHECK: vo %v24, [[REG1]], [[REG2]]
143 ; CHECK: vo %v24, [[REG1]], [[REG2]]
181 ; CHECK: vo [[REG:%v[0-9]+]], [[REG1]], [[REG2]]
243 ; CHECK: vo [[REG:%v[0-9]+]], [[REG1]], [[REG2]]
317 ; CHECK: vo [[REG:%v[0-9]+]], [[REG1]], [[REG2]]
331 ; CHECK: vo [[REG:%v[0-9]+]], [[REG1]], [[REG2]]
H A Dvec-cmp-07.ll20 ; CHECK: vo %v24, [[REG1]], [[REG2]]
143 ; CHECK: vo %v24, [[REG1]], [[REG2]]
181 ; CHECK: vo [[REG:%v[0-9]+]], [[REG1]], [[REG2]]
243 ; CHECK: vo [[REG:%v[0-9]+]], [[REG1]], [[REG2]]
317 ; CHECK: vo [[REG:%v[0-9]+]], [[REG1]], [[REG2]]
331 ; CHECK: vo [[REG:%v[0-9]+]], [[REG1]], [[REG2]]
H A Dvec-cmp-cmp-logic-select.ll46 ; CHECK-NEXT: vo %v0, [[REG2]], [[REG3]]
67 ; CHECK-DAG: vo [[REG7:%v[0-9]+]], %v2, [[REG4]]
68 ; CHECK-DAG: vo [[REG8:%v[0-9]+]], [[REG2]], [[REG3]]
108 ; CHECK-DAG: vo %v0, [[REG1]], [[REG2]]
124 ; CHECK-NEXT: vo %v0, %v0, %v1
140 ; CHECK-NEXT: vo %v0, %v0, %v1
493 ; CHECK-NEXT: vo %v0, %v0, %v1
502 ; CHECK-Z14-NEXT: vo %v0, %v0, %v1
528 ; CHECK-NEXT: vo %v0, %v0, %v1
537 ; CHECK-Z14-NEXT: vo %v0, %v0, %v1
[all …]
H A Dvec-strict-cmp-03.ll23 ; CHECK: vo %v24, [[REG1]], [[REG2]]
179 ; CHECK: vo %v24, [[REG1]], [[REG2]]
226 ; CHECK: vo [[REG:%v[0-9]+]], [[REG1]], [[REG2]]
303 ; CHECK: vo [[REG:%v[0-9]+]], [[REG1]], [[REG2]]
395 ; CHECK: vo [[REG:%v[0-9]+]], [[REG1]], [[REG2]]
412 ; CHECK: vo [[REG:%v[0-9]+]], [[REG1]], [[REG2]]
H A Dvec-strict-cmp-02.ll23 ; CHECK: vo %v24, [[REG1]], [[REG2]]
179 ; CHECK: vo %v24, [[REG1]], [[REG2]]
226 ; CHECK: vo [[REG:%v[0-9]+]], [[REG1]], [[REG2]]
303 ; CHECK: vo [[REG:%v[0-9]+]], [[REG1]], [[REG2]]
395 ; CHECK: vo [[REG:%v[0-9]+]], [[REG1]], [[REG2]]
412 ; CHECK: vo [[REG:%v[0-9]+]], [[REG1]], [[REG2]]
H A Dvec-strict-cmps-01.ll23 ; CHECK: vo %v24, [[REG1]], [[REG2]]
179 ; CHECK: vo %v24, [[REG1]], [[REG2]]
226 ; CHECK: vo [[REG:%v[0-9]+]], [[REG1]], [[REG2]]
303 ; CHECK: vo [[REG:%v[0-9]+]], [[REG1]], [[REG2]]
395 ; CHECK: vo [[REG:%v[0-9]+]], [[REG1]], [[REG2]]
412 ; CHECK: vo [[REG:%v[0-9]+]], [[REG1]], [[REG2]]
H A Dvec-strict-cmps-02.ll23 ; CHECK: vo %v24, [[REG1]], [[REG2]]
179 ; CHECK: vo %v24, [[REG1]], [[REG2]]
226 ; CHECK: vo [[REG:%v[0-9]+]], [[REG1]], [[REG2]]
303 ; CHECK: vo [[REG:%v[0-9]+]], [[REG1]], [[REG2]]
395 ; CHECK: vo [[REG:%v[0-9]+]], [[REG1]], [[REG2]]
412 ; CHECK: vo [[REG:%v[0-9]+]], [[REG1]], [[REG2]]
H A Dvec-cmp-05.ll42 ; CHECK: vo %v24, [[RES1]], [[RES0]]
275 ; CHECK: vo %v24, [[RES1]], [[RES0]]
322 ; CHECK: vo [[REG:%v[0-9]+]],
382 ; CHECK: vo [[REG:%v[0-9]+]],
454 ; CHECK: vo [[REG:%v[0-9]+]],
466 ; CHECK: vo [[REG:%v[0-9]+]],
H A Dvec-strict-cmp-01.ll45 ; CHECK: vo %v24, [[RES1]], [[RES0]]
311 ; CHECK: vo %v24, [[RES1]], [[RES0]]
367 ; CHECK: vo [[REG:%v[0-9]+]],
442 ; CHECK: vo [[REG:%v[0-9]+]],
532 ; CHECK: vo [[REG:%v[0-9]+]],
547 ; CHECK: vo [[REG:%v[0-9]+]],
H A Dvec-zext.ll100 ; CHECK-NEXT: vo %v0, %v1, %v0
/llvm-project-15.0.7/libcxx/test/std/numerics/numarray/template.valarray/valarray.assign/
H A Dvalue_assign.addressof.compile.pass.cpp23 std::valarray<operator_hijacker> vo; in test() local
25 v = vo; in test()
/llvm-project-15.0.7/libcxx/test/std/containers/sequences/vector/vector.special/
H A Dswap.addressof.compile.pass.cpp22 std::vector<operator_hijacker> vo; in test() local
24 v.swap(vo); in test()
/llvm-project-15.0.7/lldb/source/Core/
H A DValueObject.cpp3034 return (m_root = FollowParentChain([](ValueObject *vo) -> bool { in GetRoot() argument
3035 return (vo->m_parent != nullptr); in GetRoot()
3041 ValueObject *vo = this; in FollowParentChain() local
3042 while (vo) { in FollowParentChain()
3043 if (!f(vo)) in FollowParentChain()
3045 vo = vo->m_parent; in FollowParentChain()
3047 return vo; in FollowParentChain()
/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/
H A Dinterleave-crash.ll37 %vo = load <128 x i16>, <128 x i16>* %1, align 256
39 …%3 = shufflevector <128 x i16> %vo, <128 x i16> poison, <256 x i32> <i32 0, i32 1, i32 2, i32 3, i…
77 %vo = load <256 x i16>, <256 x i16>* %1, align 512
79 …%3 = shufflevector <256 x i16> %vo, <256 x i16> poison, <512 x i32> <i32 0, i32 1, i32 2, i32 3, i…
/llvm-project-15.0.7/llvm/test/MC/SystemZ/
H A Dinsn-good-z13.s5298 #CHECK: vo %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x6a]
5299 #CHECK: vo %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x02,0x6a]
5300 #CHECK: vo %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x6a]
5301 #CHECK: vo %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x6a]
5302 #CHECK: vo %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x0a,0x6a]
5304 vo %v0, %v0, %v0
5305 vo %v0, %v0, %v31
5306 vo %v0, %v31, %v0
5307 vo %v31, %v0, %v0
5308 vo %v18, %v3, %v20
H A Dinsn-bad-zEC12.s1464 #CHECK: vo %v0, %v0, %v0
1466 vo %v0, %v0, %v0
/llvm-project-15.0.7/llvm/test/MC/Disassembler/SystemZ/
H A Dinsns-z13.txt3602 # CHECK: vo %v0, %v0, %v0
3605 # CHECK: vo %v18, %v3, %v20
3608 # CHECK: vo %v31, %v31, %v31
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZInstrVector.td717 def VO : BinaryVRRc<"vo", 0xE76A, null_frag, v128any, v128any>;