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/llvm-project-15.0.7/clang/test/CodeGen/PowerPC/
H A Dbuiltins-ppc-altivec.c88 vi = vec_abs(vi); in test1()
116 vi = vec_nabs(vi); in test1()
148 vi = vec_abss(vi); in test1()
203 res_vi = vec_add(vi, vi); in test1()
231 res_vi = vec_adde(vi, vi, vi); in test1()
381 res_vi = vec_adds(vi, vi); in test1()
534 res_vi = vec_and(vi, vi); in test1()
4915 vec_st(vi, 0, &vi); in test6()
5019 vec_stvx(vi, 0, &vi); in test6()
5245 vec_stl(vi, 0, &vi); in test6()
[all …]
H A Daltivec.c33 vector int vi; in test2() local
35 vi = (vector int)(1); // CHECK: <i32 1, i32 1, i32 1, i32 1> in test2()
37 vi = (vector int)(1, 2, 3, 4); // CHECK: <i32 1, i32 2, i32 3, i32 4> in test2()
38 vi = (vector int)(1, 2, 3, 4, 5); // CHECK: <i32 1, i32 2, i32 3, i32 4> in test2()
40 vi = (vector int){1}; // CHECK: <i32 1, i32 0, i32 0, i32 0> in test2()
41 vi = (vector int){1, 2}; // CHECK: <i32 1, i32 2, i32 0, i32 0> in test2()
42 vi = (vector int){1, 2, 3, 4}; // CHECK: <i32 1, i32 2, i32 3, i32 4> in test2()
48 vector int vi; in test3() local
49 …vi++; // CHECK: add <4 x i32> {{.*}} <i32 1, i32 1, i32 1, i32 … in test3()
/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/
H A Dctlz-sdnode.ll42 ; CHECK-D-NEXT: vmseq.vi v0, v8, 0
244 ; CHECK-NEXT: vsrl.vi v8, v8, 2
273 ; CHECK-NEXT: vsrl.vi v8, v8, 2
289 ; RV32I-NEXT: vsrl.vi v9, v8, 1
291 ; RV32I-NEXT: vsrl.vi v9, v8, 2
293 ; RV32I-NEXT: vsrl.vi v9, v8, 4
295 ; RV32I-NEXT: vsrl.vi v9, v8, 8
298 ; RV32I-NEXT: vsrl.vi v9, v8, 1
306 ; RV32I-NEXT: vsrl.vi v8, v8, 2
309 ; RV32I-NEXT: vsrl.vi v9, v8, 4
[all …]
H A Dbitreverse-sdnode.ll9 ; CHECK-NEXT: vand.vi v9, v8, 15
10 ; CHECK-NEXT: vsll.vi v9, v9, 4
11 ; CHECK-NEXT: vsrl.vi v8, v8, 4
12 ; CHECK-NEXT: vand.vi v8, v8, 15
14 ; CHECK-NEXT: vsrl.vi v9, v8, 2
18 ; CHECK-NEXT: vsll.vi v8, v8, 2
20 ; CHECK-NEXT: vsrl.vi v9, v8, 1
37 ; CHECK-NEXT: vsll.vi v9, v9, 4
38 ; CHECK-NEXT: vsrl.vi v8, v8, 4
41 ; CHECK-NEXT: vsrl.vi v9, v8, 2
[all …]
H A Dfixed-vectors-ctlz.ll18 ; CHECK-NEXT: vsrl.vi v9, v8, 1
20 ; CHECK-NEXT: vsrl.vi v9, v8, 2
22 ; CHECK-NEXT: vsrl.vi v9, v8, 4
25 ; CHECK-NEXT: vsrl.vi v9, v8, 1
31 ; CHECK-NEXT: vsrl.vi v8, v8, 2
34 ; CHECK-NEXT: vsrl.vi v9, v8, 4
36 ; CHECK-NEXT: vand.vi v8, v8, 15
51 ; LMULMAX8-NEXT: vmseq.vi v0, v8, 0
241 ; LMULMAX8-NEXT: vmseq.vi v0, v8, 0
783 ; LMULMAX2-NEXT: vsrl.vi v8, v8, 2
[all …]
H A Dfixed-vectors-bitreverse.ll12 ; RV32-NEXT: vsrl.vi v9, v8, 8
13 ; RV32-NEXT: vsll.vi v8, v8, 8
15 ; RV32-NEXT: vsrl.vi v9, v8, 4
20 ; RV32-NEXT: vsll.vi v8, v8, 4
22 ; RV32-NEXT: vsrl.vi v9, v8, 2
27 ; RV32-NEXT: vsll.vi v8, v8, 2
29 ; RV32-NEXT: vsrl.vi v9, v8, 1
43 ; RV64-NEXT: vsrl.vi v9, v8, 8
44 ; RV64-NEXT: vsll.vi v8, v8, 8
46 ; RV64-NEXT: vsrl.vi v9, v8, 4
[all …]
H A Dctpop-sdnode.ll9 ; CHECK-NEXT: vsrl.vi v9, v8, 1
15 ; CHECK-NEXT: vsrl.vi v8, v8, 2
18 ; CHECK-NEXT: vsrl.vi v9, v8, 4
20 ; CHECK-NEXT: vand.vi v8, v8, 15
31 ; CHECK-NEXT: vsrl.vi v9, v8, 1
37 ; CHECK-NEXT: vsrl.vi v8, v8, 2
40 ; CHECK-NEXT: vsrl.vi v9, v8, 4
42 ; CHECK-NEXT: vand.vi v8, v8, 15
53 ; CHECK-NEXT: vsrl.vi v9, v8, 1
59 ; CHECK-NEXT: vsrl.vi v8, v8, 2
[all …]
H A Dbswap-sdnode.ll9 ; CHECK-NEXT: vsrl.vi v9, v8, 8
10 ; CHECK-NEXT: vsll.vi v8, v8, 8
22 ; CHECK-NEXT: vsrl.vi v9, v8, 8
23 ; CHECK-NEXT: vsll.vi v8, v8, 8
35 ; CHECK-NEXT: vsrl.vi v9, v8, 8
36 ; CHECK-NEXT: vsll.vi v8, v8, 8
49 ; CHECK-NEXT: vsll.vi v8, v8, 8
62 ; CHECK-NEXT: vsll.vi v8, v8, 8
87 ; RV32-NEXT: vsrl.vi v9, v8, 8
104 ; RV64-NEXT: vsrl.vi v9, v8, 8
[all …]
H A Dfixed-vectors-ctpop.ll12 ; CHECK-NEXT: vsrl.vi v9, v8, 1
18 ; CHECK-NEXT: vsrl.vi v8, v8, 2
21 ; CHECK-NEXT: vsrl.vi v9, v8, 4
23 ; CHECK-NEXT: vand.vi v8, v8, 15
39 ; LMULMAX2-RV32-NEXT: vsrl.vi v9, v8, 1
412 ; LMULMAX2-NEXT: vsrl.vi v10, v8, 1
418 ; LMULMAX2-NEXT: vsrl.vi v8, v8, 2
421 ; LMULMAX2-NEXT: vsrl.vi v10, v8, 4
423 ; LMULMAX2-NEXT: vand.vi v8, v8, 15
439 ; LMULMAX1-NEXT: vsrl.vi v8, v8, 2
[all …]
H A Dinsertelt-i1.ll13 ; CHECK-NEXT: vslideup.vi v9, v8, 2
15 ; CHECK-NEXT: vand.vi v8, v9, 1
16 ; CHECK-NEXT: vmsne.vi v0, v8, 0
33 ; CHECK-NEXT: vand.vi v8, v9, 1
34 ; CHECK-NEXT: vmsne.vi v0, v8, 0
50 ; CHECK-NEXT: vand.vi v8, v9, 1
51 ; CHECK-NEXT: vmsne.vi v0, v8, 0
68 ; CHECK-NEXT: vand.vi v8, v9, 1
69 ; CHECK-NEXT: vmsne.vi v0, v8, 0
85 ; CHECK-NEXT: vand.vi v8, v9, 1
[all …]
H A Dfixed-vectors-bswap.ll12 ; CHECK-NEXT: vsrl.vi v9, v8, 8
13 ; CHECK-NEXT: vsll.vi v8, v8, 8
30 ; RV32-NEXT: vsrl.vi v9, v8, 8
34 ; RV32-NEXT: vsrl.vi v10, v8, 24
36 ; RV32-NEXT: vsll.vi v10, v8, 8
39 ; RV32-NEXT: vsll.vi v8, v8, 24
49 ; RV64-NEXT: vsrl.vi v9, v8, 8
53 ; RV64-NEXT: vsrl.vi v10, v8, 24
55 ; RV64-NEXT: vsll.vi v10, v8, 8
58 ; RV64-NEXT: vsll.vi v8, v8, 24
[all …]
H A Dfixed-vectors-insert-i1.ll13 ; CHECK-NEXT: vmsne.vi v0, v8, 0
30 ; RV32-NEXT: vand.vi v8, v9, 1
31 ; RV32-NEXT: vmsne.vi v0, v8, 0
45 ; RV64-NEXT: vand.vi v8, v9, 1
46 ; RV64-NEXT: vmsne.vi v0, v8, 0
62 ; CHECK-NEXT: vand.vi v8, v9, 1
80 ; RV32-NEXT: vand.vi v8, v9, 1
81 ; RV32-NEXT: vmsne.vi v0, v8, 0
95 ; RV64-NEXT: vand.vi v8, v9, 1
130 ; RV32-NEXT: vand.vi v8, v9, 1
[all …]
H A Dcttz-sdnode.ll32 ; CHECK-D-NEXT: vrsub.vi v9, v8, 0
42 ; CHECK-D-NEXT: vmseq.vi v0, v8, 0
241 ; CHECK-NEXT: vsrl.vi v8, v8, 2
267 ; CHECK-NEXT: vsrl.vi v8, v8, 2
287 ; RV32I-NEXT: vsrl.vi v9, v8, 1
295 ; RV32I-NEXT: vsrl.vi v8, v8, 2
298 ; RV32I-NEXT: vsrl.vi v9, v8, 4
305 ; RV32I-NEXT: vsrl.vi v8, v8, 8
315 ; RV64I-NEXT: vsrl.vi v9, v8, 1
323 ; RV64I-NEXT: vsrl.vi v8, v8, 2
[all …]
H A Dfixed-vectors-fp2i.ll40 ; CHECK-NEXT: vand.vi v8, v9, 1
41 ; CHECK-NEXT: vmsne.vi v0, v8, 0
74 ; CHECK-NEXT: vand.vi v8, v9, 1
75 ; CHECK-NEXT: vmsne.vi v0, v8, 0
346 ; CHECK-NEXT: vand.vi v8, v9, 1
347 ; CHECK-NEXT: vmsne.vi v0, v8, 0
358 ; CHECK-NEXT: vand.vi v8, v9, 1
359 ; CHECK-NEXT: vmsne.vi v0, v8, 0
406 ; CHECK-NEXT: vand.vi v8, v9, 1
407 ; CHECK-NEXT: vmsne.vi v0, v8, 0
[all …]
H A Dfixed-vectors-cttz.ll22 ; CHECK-NEXT: vsrl.vi v9, v8, 1
28 ; CHECK-NEXT: vsrl.vi v8, v8, 2
31 ; CHECK-NEXT: vsrl.vi v9, v8, 4
33 ; CHECK-NEXT: vand.vi v8, v8, 15
41 ; LMULMAX8-NEXT: vrsub.vi v9, v8, 0
51 ; LMULMAX8-NEXT: vmseq.vi v0, v8, 0
221 ; LMULMAX8-NEXT: vrsub.vi v9, v8, 0
227 ; LMULMAX8-NEXT: vmseq.vi v0, v8, 0
684 ; LMULMAX2-NEXT: vsrl.vi v8, v8, 2
709 ; LMULMAX1-NEXT: vsrl.vi v8, v8, 2
[all …]
H A Dfixed-vectors-stepvector-rv64.ll108 ; LMULMAX1-NEXT: vadd.vi v9, v8, 8
151 ; LMULMAX1-NEXT: vadd.vi v9, v8, 4
170 ; LMULMAX1-NEXT: vadd.vi v9, v8, 4
171 ; LMULMAX1-NEXT: vadd.vi v10, v8, 8
179 ; LMULMAX2-NEXT: vadd.vi v10, v8, 8
204 ; LMULMAX1-NEXT: vadd.vi v9, v8, 2
223 ; LMULMAX1-NEXT: vadd.vi v9, v8, 2
224 ; LMULMAX1-NEXT: vadd.vi v10, v8, 4
225 ; LMULMAX1-NEXT: vadd.vi v11, v8, 6
232 ; LMULMAX2-NEXT: vadd.vi v10, v8, 4
[all …]
H A Dfixed-vector-trunc-vp-mask.ll11 ; CHECK-NEXT: vand.vi v8, v8, 1, v0.t
13 ; CHECK-NEXT: vmsne.vi v0, v8, 0, v0.t
23 ; CHECK-NEXT: vand.vi v8, v8, 1
24 ; CHECK-NEXT: vmsne.vi v0, v8, 0
36 ; CHECK-NEXT: vand.vi v8, v8, 1, v0.t
38 ; CHECK-NEXT: vmsne.vi v0, v8, 0, v0.t
48 ; CHECK-NEXT: vand.vi v8, v8, 1
49 ; CHECK-NEXT: vmsne.vi v0, v8, 0
61 ; CHECK-NEXT: vand.vi v8, v8, 1, v0.t
73 ; CHECK-NEXT: vand.vi v8, v8, 1
[all …]
H A Dfixed-vectors-extract-subvector.ll25 ; CHECK-NEXT: vslidedown.vi v8, v8, 2
488 ; CHECK-NEXT: vmsne.vi v8, v9, 0
505 ; CHECK-NEXT: vmsne.vi v0, v8, 0
513 ; CHECK-NEXT: vmsne.vi v8, v9, 0
532 ; CHECK-NEXT: vmsne.vi v8, v9, 0
549 ; CHECK-NEXT: vmsne.vi v0, v8, 0
557 ; CHECK-NEXT: vmsne.vi v8, v9, 0
575 ; CHECK-NEXT: vmsne.vi v0, v8, 0
583 ; CHECK-NEXT: vmsne.vi v8, v9, 0
600 ; CHECK-NEXT: vmsne.vi v0, v8, 0
[all …]
H A Dfixed-vectors-abs.ll12 ; CHECK-NEXT: vrsub.vi v9, v8, 0
28 ; CHECK-NEXT: vrsub.vi v9, v8, 0
44 ; CHECK-NEXT: vrsub.vi v9, v8, 0
60 ; CHECK-NEXT: vrsub.vi v9, v8, 0
77 ; LMULMAX2-NEXT: vrsub.vi v10, v8, 0
88 ; LMULMAX1-RV32-NEXT: vrsub.vi v10, v8, 0
90 ; LMULMAX1-RV32-NEXT: vrsub.vi v10, v9, 0
102 ; LMULMAX1-RV64-NEXT: vrsub.vi v10, v8, 0
121 ; LMULMAX2-NEXT: vrsub.vi v10, v8, 0
165 ; LMULMAX2-NEXT: vrsub.vi v10, v8, 0
[all …]
/llvm-project-15.0.7/clang/test/SemaCXX/
H A Daltivec.cpp14 vector int vi; in test_vec_step() local
29 int res10[vec_step(vi) == 4 ? 1 : -1]; in test_vec_step()
57 vector int vi; in test2() local
58 ++vi; in test2()
59 vi++; in test2()
60 --vi; in test2()
61 vi--; in test2()
65 ++vi=vi; // expected-warning {{unsequenced}} in test2()
66 (++vi)[1]=1; in test2()
67 template_f(vi); in test2()
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dunaligned_load_store_vector.ll11 %vi = bitcast i8* %pi to <8 x i8>*
29 %vi = bitcast i8* %pi to <4 x i16>*
47 %vi = bitcast i8* %pi to <2 x i32>*
65 %vi = bitcast i8* %pi to <2 x float>*
83 %vi = bitcast i8* %pi to <16 x i8>*
101 %vi = bitcast i8* %pi to <8 x i16>*
119 %vi = bitcast i8* %pi to <4 x i32>*
137 %vi = bitcast i8* %pi to <2 x i64>*
173 %vi = bitcast i8* %pi to <8 x i8>*
191 %vi = bitcast i8* %pi to <4 x i16>*
[all …]
/llvm-project-15.0.7/clang/test/Sema/
H A Daltivec-init.c13 vector int vi; in foo() local
14 vi = (vector int)(1); in foo()
15 …vi = (vector int)(1, 2); // expected-error {{number of elements must be either one or mat… in foo()
16 vi = (vector int)(1, 2, 3, 4); in foo()
17 vi = (vector int)(1, 2, 3, 4, 5); // expected-warning {{excess elements in vector initializer}} in foo()
18 vi = (vector int){1}; in foo()
19 vi = (vector int){1, 2}; in foo()
20 vi = (vector int){1, 2, 3, 4, 5}; // expected-warning {{excess elements in vector initializer}} in foo()
H A Dext_vector_casts.c99 int4 vi = i; in splats() local
109 vi = l + vi; // expected-warning {{implicit conversion loses integer precision}} in splats()
110 vi = 1 + vi; in splats()
111 vi = vi + 2.0; // expected-error {{cannot convert between vector values of different size}} in splats()
112 vi = vi + 0xffffffff; // expected-warning {{implicit conversion changes signedness}} in splats()
/llvm-project-15.0.7/clang/include/clang/Basic/
H A DBuiltinsNVPTX.def539 BUILTIN(__nvvm_bar_sync, "vi", "n")
816 TARGET_BUILTIN(__hmma_m16n16k16_ld_a, "vi*iC*UiIi", "", AND(SM_70,PTX60))
817 TARGET_BUILTIN(__hmma_m16n16k16_ld_b, "vi*iC*UiIi", "", AND(SM_70,PTX60))
823 TARGET_BUILTIN(__hmma_m32n8k16_ld_a, "vi*iC*UiIi", "", AND(SM_70,PTX61))
824 TARGET_BUILTIN(__hmma_m32n8k16_ld_b, "vi*iC*UiIi", "", AND(SM_70,PTX61))
830 TARGET_BUILTIN(__hmma_m8n32k16_ld_a, "vi*iC*UiIi", "", AND(SM_70,PTX61))
831 TARGET_BUILTIN(__hmma_m8n32k16_ld_b, "vi*iC*UiIi", "", AND(SM_70,PTX61))
855 TARGET_BUILTIN(__bmma_m8n8k128_ld_c, "vi*iC*UiIi", "", AND(SM_75,PTX63))
871 TARGET_BUILTIN(__imma_m32n8k16_ld_c, "vi*iC*UiIi", "", AND(SM_72,PTX63))
879 TARGET_BUILTIN(__imma_m8n32k16_ld_c, "vi*iC*UiIi", "", AND(SM_72,PTX63))
[all …]
/llvm-project-15.0.7/llvm/test/MC/RISCV/rvv/
H A Dcompare.s47 vmseq.vi v8, v4, 15
83 vmsne.vi v8, v4, 15
167 vmsleu.vi v8, v4, 15
203 vmsle.vi v8, v4, 15
227 vmsgtu.vi v8, v4, 15
251 vmsgt.vi v8, v4, 15
311 vmsltu.vi v8, v4, 16
323 vmsltu.vi v8, v4, 0
335 vmslt.vi v8, v4, 16
359 vmsgeu.vi v8, v4, 0
[all …]

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