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/llvm-project-15.0.7/llvm/test/Transforms/WholeProgramDevirt/
H A Dexport-single-impl.ll55 ; SUMMARY-NEXT: SingleImplName: vf4.llvm.merged
60 ; CHECK: $vf4.llvm.merged = comdat largest
61 $vf4 = comdat largest
71 ; CHECK: @vt4 = constant void (i8*)* @vf4.llvm.merged, comdat($vf4.llvm.merged)
72 @vt4 = constant void (i8*)* @vf4, comdat($vf4), !type !3
89 ; CHECK: define hidden void @vf4.llvm.merged(i8* %0) comdat {
90 define internal void @vf4(i8*) comdat {
H A Dconstant-arg.ll8 …x i8] c"\00\00\00\00\00\00\00\01", [1 x i8*] [i8* bitcast (i1 (i8*, i32)* @vf4 to i8*)], [0 x i8] …
13 @vt4 = constant [1 x i8*] [i8* bitcast (i1 (i8*, i32)* @vf4 to i8*)], !type !0
28 define i1 @vf4(i8* %this, i32 %arg) readnone {
H A Dvcp-too-wide-ints.ll9 @vt4 = constant [1 x i8*] [i8* bitcast (i128 (i8*, i64)* @vf4 to i8*)], !type !1
26 define i128 @vf4(i8* %this, i64 %arg) readnone {
/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/
H A Dfixed-vectors-int-exttrunc.ll14 ; CHECK-NEXT: vsext.vf4 v9, v8
28 ; CHECK-NEXT: vzext.vf4 v9, v8
42 ; LMULMAX8-NEXT: vsext.vf4 v10, v8
50 ; LMULMAX2-NEXT: vsext.vf4 v10, v8
61 ; LMULMAX1-NEXT: vsext.vf4 v10, v9
62 ; LMULMAX1-NEXT: vsext.vf4 v9, v8
79 ; LMULMAX8-NEXT: vsext.vf4 v16, v8
98 ; LMULMAX2-NEXT: vsext.vf4 v14, v8
99 ; LMULMAX2-NEXT: vsext.vf4 v8, v10
137 ; LMULMAX1-NEXT: vsext.vf4 v12, v8
[all …]
H A Dvexts-sdnode.ll31 ; CHECK-NEXT: vsext.vf4 v9, v8
42 ; CHECK-NEXT: vzext.vf4 v9, v8
97 ; CHECK-NEXT: vsext.vf4 v9, v8
108 ; CHECK-NEXT: vzext.vf4 v9, v8
163 ; CHECK-NEXT: vsext.vf4 v10, v8
174 ; CHECK-NEXT: vzext.vf4 v10, v8
229 ; CHECK-NEXT: vsext.vf4 v12, v8
240 ; CHECK-NEXT: vzext.vf4 v12, v8
295 ; CHECK-NEXT: vsext.vf4 v16, v8
361 ; CHECK-NEXT: vsext.vf4 v9, v8
[all …]
H A Dfixed-vectors-extload-truncstore.ll49 ; CHECK-NEXT: vsext.vf4 v8, v9
61 ; CHECK-NEXT: vzext.vf4 v8, v9
121 ; CHECK-NEXT: vsext.vf4 v8, v9
133 ; CHECK-NEXT: vzext.vf4 v8, v9
218 ; LMULMAX1-NEXT: vsext.vf4 v9, v8
219 ; LMULMAX1-NEXT: vsext.vf4 v8, v10
226 ; LMULMAX4-NEXT: vsext.vf4 v8, v10
241 ; LMULMAX1-NEXT: vzext.vf4 v9, v8
242 ; LMULMAX1-NEXT: vzext.vf4 v8, v10
590 ; CHECK-NEXT: vsext.vf4 v8, v9
[all …]
H A Dvsext-vp.ll35 ; CHECK-NEXT: vsext.vf4 v9, v8, v0.t
46 ; CHECK-NEXT: vsext.vf4 v9, v8
107 ; CHECK-NEXT: vsext.vf4 v10, v8, v0.t
118 ; CHECK-NEXT: vsext.vf4 v10, v8
167 ; CHECK-NEXT: vsext.vf4 v16, v10, v0.t
174 ; CHECK-NEXT: vsext.vf4 v24, v8, v0.t
194 ; CHECK-NEXT: vsext.vf4 v24, v8
200 ; CHECK-NEXT: vsext.vf4 v16, v10
H A Dvzext-vp.ll35 ; CHECK-NEXT: vzext.vf4 v9, v8, v0.t
46 ; CHECK-NEXT: vzext.vf4 v9, v8
107 ; CHECK-NEXT: vzext.vf4 v10, v8, v0.t
118 ; CHECK-NEXT: vzext.vf4 v10, v8
167 ; CHECK-NEXT: vzext.vf4 v16, v10, v0.t
174 ; CHECK-NEXT: vzext.vf4 v24, v8, v0.t
194 ; CHECK-NEXT: vzext.vf4 v24, v8
200 ; CHECK-NEXT: vzext.vf4 v16, v10
H A Dfixed-vectors-i2fp.ll54 ; CHECK-NEXT: vsext.vf4 v9, v8
68 ; CHECK-NEXT: vzext.vf4 v9, v8
206 ; CHECK-NEXT: vsext.vf4 v9, v8
221 ; CHECK-NEXT: vzext.vf4 v9, v8
236 ; LMULMAX8-NEXT: vsext.vf4 v12, v8
248 ; LMULMAX1-NEXT: vsext.vf4 v10, v9
255 ; LMULMAX1-NEXT: vsext.vf4 v12, v11
259 ; LMULMAX1-NEXT: vsext.vf4 v12, v8
280 ; LMULMAX8-NEXT: vzext.vf4 v12, v8
292 ; LMULMAX1-NEXT: vzext.vf4 v10, v9
[all …]
H A Dvpgather-sdnode.ll95 ; RV32-NEXT: vsext.vf4 v8, v9
103 ; RV64-NEXT: vsext.vf4 v8, v10
116 ; RV32-NEXT: vzext.vf4 v8, v9
124 ; RV64-NEXT: vzext.vf4 v8, v10
237 ; RV32-NEXT: vsext.vf4 v12, v8
272 ; RV32-NEXT: vsext.vf4 v24, v10
280 ; RV32-NEXT: vsext.vf4 v24, v8
443 ; RV32-NEXT: vsext.vf4 v8, v10
451 ; RV64-NEXT: vsext.vf4 v8, v10
464 ; RV32-NEXT: vzext.vf4 v8, v10
[all …]
H A Dfixed-vectors-vpgather.ll75 ; RV32-NEXT: vsext.vf4 v8, v9
83 ; RV64-NEXT: vsext.vf4 v8, v9
96 ; RV32-NEXT: vzext.vf4 v8, v9
104 ; RV64-NEXT: vzext.vf4 v8, v9
257 ; RV32-NEXT: vsext.vf4 v10, v8
281 ; RV32-NEXT: vsext.vf4 v16, v8
390 ; RV32-NEXT: vsext.vf4 v8, v9
398 ; RV64-NEXT: vsext.vf4 v8, v9
411 ; RV32-NEXT: vzext.vf4 v8, v9
419 ; RV64-NEXT: vzext.vf4 v8, v9
[all …]
H A Dvzext.ll191 ; CHECK-NEXT: vzext.vf4 v9, v8
214 ; CHECK-NEXT: vzext.vf4 v8, v9, v0.t
235 ; CHECK-NEXT: vzext.vf4 v10, v8
279 ; CHECK-NEXT: vzext.vf4 v12, v8
323 ; CHECK-NEXT: vzext.vf4 v16, v8
367 ; CHECK-NEXT: vzext.vf4 v9, v8
390 ; CHECK-NEXT: vzext.vf4 v8, v9, v0.t
411 ; CHECK-NEXT: vzext.vf4 v9, v8
455 ; CHECK-NEXT: vzext.vf4 v10, v8
499 ; CHECK-NEXT: vzext.vf4 v12, v8
[all …]
H A Dvsext.ll191 ; CHECK-NEXT: vsext.vf4 v9, v8
214 ; CHECK-NEXT: vsext.vf4 v8, v9, v0.t
235 ; CHECK-NEXT: vsext.vf4 v10, v8
279 ; CHECK-NEXT: vsext.vf4 v12, v8
323 ; CHECK-NEXT: vsext.vf4 v16, v8
367 ; CHECK-NEXT: vsext.vf4 v9, v8
390 ; CHECK-NEXT: vsext.vf4 v8, v9, v0.t
411 ; CHECK-NEXT: vsext.vf4 v9, v8
455 ; CHECK-NEXT: vsext.vf4 v10, v8
499 ; CHECK-NEXT: vsext.vf4 v12, v8
[all …]
H A Dvpscatter-sdnode.ll176 ; RV32-NEXT: vsext.vf4 v12, v9
333 ; RV32-NEXT: vsext.vf4 v12, v10
356 ; RV32-NEXT: vsext.vf4 v12, v10
380 ; RV32-NEXT: vzext.vf4 v12, v10
413 ; RV64-NEXT: vsext.vf4 v16, v10
538 ; RV32-NEXT: vsext.vf4 v16, v12
561 ; RV32-NEXT: vsext.vf4 v16, v12
585 ; RV32-NEXT: vzext.vf4 v16, v12
618 ; RV64-NEXT: vsext.vf4 v16, v12
641 ; RV64-NEXT: vsext.vf4 v16, v12
[all …]
H A Dmscatter-sdnode.ll178 ; RV32-NEXT: vsext.vf4 v12, v9
339 ; RV32-NEXT: vsext.vf4 v12, v10
362 ; RV32-NEXT: vsext.vf4 v12, v10
386 ; RV32-NEXT: vzext.vf4 v12, v10
419 ; RV64-NEXT: vsext.vf4 v16, v10
550 ; RV32-NEXT: vsext.vf4 v16, v12
572 ; RV32-NEXT: vsext.vf4 v16, v12
595 ; RV32-NEXT: vzext.vf4 v16, v12
626 ; RV64-NEXT: vsext.vf4 v16, v12
648 ; RV64-NEXT: vsext.vf4 v16, v12
[all …]
H A Dfixed-vectors-zext-vp.ll37 ; CHECK-NEXT: vzext.vf4 v9, v8, v0.t
48 ; CHECK-NEXT: vzext.vf4 v9, v8
109 ; CHECK-NEXT: vzext.vf4 v10, v8, v0.t
120 ; CHECK-NEXT: vzext.vf4 v10, v8
H A Dfixed-vectors-sext-vp.ll37 ; CHECK-NEXT: vsext.vf4 v9, v8, v0.t
48 ; CHECK-NEXT: vsext.vf4 v9, v8
109 ; CHECK-NEXT: vsext.vf4 v10, v8, v0.t
120 ; CHECK-NEXT: vsext.vf4 v10, v8
H A Dmgather-sdnode.ll95 ; RV32-NEXT: vsext.vf4 v8, v9
103 ; RV64-NEXT: vsext.vf4 v8, v10
116 ; RV32-NEXT: vzext.vf4 v8, v9
124 ; RV64-NEXT: vzext.vf4 v8, v10
253 ; RV32-NEXT: vsext.vf4 v12, v8
360 ; RV32-NEXT: vsext.vf4 v10, v9
369 ; RV64-NEXT: vsext.vf4 v8, v10
382 ; RV32-NEXT: vzext.vf4 v10, v9
391 ; RV64-NEXT: vzext.vf4 v8, v10
476 ; RV32-NEXT: vsext.vf4 v12, v8
[all …]
/llvm-project-15.0.7/llvm/test/MC/RISCV/rvv/
H A Dext.s35 vzext.vf4 v8, v4, v0.t
36 # CHECK-INST: vzext.vf4 v8, v4, v0.t
41 vzext.vf4 v8, v4
42 # CHECK-INST: vzext.vf4 v8, v4
47 vsext.vf4 v8, v4, v0.t
48 # CHECK-INST: vsext.vf4 v8, v4, v0.t
53 vsext.vf4 v8, v4
54 # CHECK-INST: vsext.vf4 v8, v4
/llvm-project-15.0.7/llvm/test/tools/UpdateTestChecks/update_analyze_test_checks/Inputs/
H A Dx86-filter-with-spaces.ll.filter.expected1 …ssertions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --filter "vf4 ="
6 ; SSE2: Cost Model: Found an estimated cost of 18 for instruction: %vf4 = shufflevector <4 x i64> …
9 …%vf4 = shufflevector <4 x i64> undef, <4 x i64> poison, <8 x i32> <i32 0, i32 0, i32 1, i32 1, i32…
H A Dx86-filter.ll.filter.expected1 …ions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --filter "(vf4|vf16)"
6 ; SSE2: Cost Model: Found an estimated cost of 18 for instruction: %vf4 = shufflevector <4 x i64> …
10 …%vf4 = shufflevector <4 x i64> undef, <4 x i64> poison, <8 x i32> <i32 0, i32 0, i32 1, i32 1, i32…
/llvm-project-15.0.7/llvm/test/tools/UpdateTestChecks/update_analyze_test_checks/
H A Dfilter-with-spaces.test4 # RUN: cp -f %S/Inputs/x86-filter-with-spaces.ll %t.ll && %update_analyze_test_checks --filter="vf4…
8 # RUN: %update_analyze_test_checks --filter="vf4 =" %t.ll
H A Dfilter.test4 # RUN: cp -f %S/Inputs/x86-filter.ll %t.ll && %update_analyze_test_checks --filter="(vf4|vf16)" %t.…
8 # RUN: %update_analyze_test_checks --filter="(vf4|vf16)" %t.ll
/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A Dvsx-minmax.ll13 @vf4 = common global <4 x float> zeroinitializer, align 16
48 store <4 x float> %15, <4 x float>* @vf4, align 16
85 ;vector float vf1, vf2, vf3, vf4;
95 ; vf4 = vec_vminfp(vf, vf);
/llvm-project-15.0.7/llvm/test/Analysis/CostModel/X86/
H A Dshuffle-replication-i64.ll15 ; SSE2-NEXT: Cost Model: Found an estimated cost of 18 for instruction: %vf4 = shufflevector <4 x …
22 ; SSE3-NEXT: Cost Model: Found an estimated cost of 18 for instruction: %vf4 = shufflevector <4 x …
29 ; SSSE3-NEXT: Cost Model: Found an estimated cost of 18 for instruction: %vf4 = shufflevector <4 x…
36 ; SSE41-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %vf4 = shufflevector <4 x…
43 ; SSE42-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %vf4 = shufflevector <4 x…
50 ; AVX-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %vf4 = shufflevector <4 x i…
57 ; AVX512FVEC512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %vf4 = shufflevect…
64 ; AVX512FVEC256-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %vf4 = shufflevect…
70 …%vf4 = shufflevector <4 x i64> undef, <4 x i64> poison, <8 x i32> <i32 0, i32 0, i32 1, i32 1, i32…
134 …%vf4 = shufflevector <4 x i64> undef, <4 x i64> poison, <12 x i32> <i32 0, i32 0, i32 0, i32 1, i3…
[all …]

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