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/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dneon-extract.ll8 ret <8 x i8> %vext
16 ret <4 x i16> %vext
24 ret <2 x i32> %vext
32 ret <1 x i64> %vext
40 ret <16 x i8> %vext
48 ret <8 x i16> %vext
56 ret <4 x i32> %vext
64 ret <2 x i64> %vext
72 ret <8 x i8> %vext
80 ret <4 x i16> %vext
[all …]
H A Darm64-vext.ll16 store <8 x i8> %vext, <8 x i8>* %xS8x8, align 8
33 store <8 x i8> %vext, <8 x i8>* %xU8x8, align 8
50 store <8 x i8> %vext, <8 x i8>* %xP8x8, align 8
71 store <4 x i16> %vext, <4 x i16>* %xS16x4, align 8
92 store <4 x i16> %vext, <4 x i16>* %xU16x4, align 8
113 store <4 x i16> %vext, <4 x i16>* %xP16x4, align 8
134 store <2 x i32> %vext, <2 x i32>* %xS32x2, align 8
155 store <2 x i32> %vext, <2 x i32>* %xU32x2, align 8
198 store <1 x i64> %vext, <1 x i64>* %xS64x1, align 8
220 store <1 x i64> %vext, <1 x i64>* %xU64x1, align 8
[all …]
H A Darm64-EXT-undef-mask.ll7 …%vext = shufflevector <8 x i16> <i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef,…
8 ret <8 x i16> %vext
14 …%vext = shufflevector <8 x i16> %in, <8 x i16> <i16 undef, i16 undef, i16 undef, i16 undef, i16 un…
15 ret <8 x i16> %vext
21 …%vext = shufflevector <8 x i8> %in, <8 x i8> <i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8…
22 ret <8 x i8> %vext
H A Darm64-ext.ll90 …%vext = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <8 x i32> <i32 undef, i32 undef, i32 undef…
91 ret <8 x i16> %vext;
H A Dmachine-copy-prop.ll73 …%vext = shufflevector <8 x i8> <i8 undef, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>, <8 x i…
74 %t6 = bitcast <8 x i8> %vext to <2 x i32>
H A Darm64-vext_reverse.ll4 ; of vext by enumerating all cases of using two undefs in shuffle masks.
/llvm-project-15.0.7/llvm/test/MC/ARM/
H A Dneon-shuffle-encoding.s3 vext.8 d16, d17, d16, #3
5 vext.8 q8, q9, q8, #3
6 vext.8 q8, q9, q8, #7
8 vext.32 q8, q9, q8, #3
11 vext.8 d17, d16, #3
12 vext.8 d7, d11, #5
13 vext.8 q3, q8, #3
14 vext.8 q9, q4, #7
15 vext.16 d1, d26, #3
16 vext.32 q5, q8, #3
[all …]
H A Dneont2-shuffle-encoding.s5 @ CHECK: vext.8 d16, d17, d16, #3 @ encoding: [0xf1,0xef,0xa0,0x03]
6 vext.8 d16, d17, d16, #3
7 @ CHECK: vext.8 d16, d17, d16, #5 @ encoding: [0xf1,0xef,0xa0,0x05]
8 vext.8 d16, d17, d16, #5
9 @ CHECK: vext.8 q8, q9, q8, #3 @ encoding: [0xf2,0xef,0xe0,0x03]
10 vext.8 q8, q9, q8, #3
11 @ CHECK: vext.8 q8, q9, q8, #7 @ encoding: [0xf2,0xef,0xe0,0x07]
12 vext.8 q8, q9, q8, #7
13 @ CHECK: vext.16 d16, d17, d16, #3 @ encoding: [0xf1,0xef,0xa0,0x06]
14 vext.16 d16, d17, d16, #3
[all …]
H A Dneont2-sub-encoding.s3 @ CHECK: vext.8 d16, d17, d16, #3 @ encoding: [0xf1,0xef,0xa0,0x03]
4 vext.8 d16, d17, d16, #3
5 @ CHECK: vext.8 d16, d17, d16, #5 @ encoding: [0xf1,0xef,0xa0,0x05]
6 vext.8 d16, d17, d16, #5
7 @ CHECK: vext.8 q8, q9, q8, #3 @ encoding: [0xf2,0xef,0xe0,0x03]
8 vext.8 q8, q9, q8, #3
9 @ CHECK: vext.8 q8, q9, q8, #7 @ encoding: [0xf2,0xef,0xe0,0x07]
10 vext.8 q8, q9, q8, #7
11 @ CHECK: vext.16 d16, d17, d16, #3 @ encoding: [0xf1,0xef,0xa0,0x06]
12 vext.16 d16, d17, d16, #3
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Ddomain-conv-vmovs.ll8 ; CHECK: vext.32 d1, d1, d0, #1
9 ; CHECK: vext.32 d1, d1, d1, #1
20 ; CHECK: vext.32 d1, d1, d1, #1
21 ; CHECK: vext.32 d1, d1, d0, #1
32 ; CHECK: vext.32 d1, d1, d1, #1
33 ; CHECK: vext.32 d1, d0, d1, #1
44 ; CHECK: vext.32 d1, d0, d1, #1
45 ; CHECK: vext.32 d1, d1, d1, #1
82 ; CHECK: vext.32
83 ; CHECK: vext.32
H A Dfp16-insert-extract.ll178 ; CHECKHARD-NEXT: vext.16 d17, d4, d5, #2
180 ; CHECKHARD-NEXT: vext.16 d16, d16, d3, #1
181 ; CHECKHARD-NEXT: vext.16 d16, d17, d16, #2
211 ; CHECKHARD-NEXT: vext.16 d18, d0, d1, #2
215 ; CHECKHARD-NEXT: vext.16 d19, d18, d2, #3
217 ; CHECKHARD-NEXT: vext.16 d18, d2, d18, #1
236 ; CHECKSOFT-NEXT: vext.16 d17, d4, d5, #2
238 ; CHECKSOFT-NEXT: vext.16 d16, d16, d3, #1
269 ; CHECKSOFT-NEXT: vext.16 d18, d0, d1, #2
273 ; CHECKSOFT-NEXT: vext.16 d19, d18, d2, #3
[all …]
H A Dvext.ll9 ; CHECK-NEXT: vext.8 d16, d17, d16, #3
23 ; CHECK-NEXT: vext.8 d16, d17, d16, #5
37 ; CHECK-NEXT: vext.8 q8, q9, q8, #3
52 ; CHECK-NEXT: vext.8 q8, q9, q8, #7
67 ; CHECK-NEXT: vext.16 d16, d17, d16, #3
81 ; CHECK-NEXT: vext.32 q8, q9, q8, #3
98 ; CHECK-NEXT: vext.8 d16, d17, d16, #3
112 ; CHECK-NEXT: vext.8 q8, q9, q8, #7
127 ; CHECK-NEXT: vext.8 q8, q8, q8, #2
154 ; CHECK-NEXT: vext.8 q8, q8, q8, #2
[all …]
H A Ddeps-fix.ll8 ; CHECK: vext
9 ; CHECK: vext
H A Dvector-DAGCombine.ll236 ; Test that we are generating vrev and vext for reverse shuffles of v8i16
243 ; CHECK-NEXT: vext.16 q8, q8, q8, #4
253 ; Test that we are generating vrev and vext for reverse shuffles of v16i8
260 ; CHECK-NEXT: vext.8 q8, q8, q8, #8
H A Dvzip.ll340 ; CHECK-NEXT: vext.32 q8, q8, q8, #2
354 ; CHECK-NEXT: vext.16 d18, d16, d17, #1
355 ; CHECK-NEXT: vext.16 d16, d18, d17, #2
356 ; CHECK-NEXT: vext.16 d16, d16, d16, #1
H A Dneon-vmovn.ll268 ; CHECK-NEXT: vext.32 q8, q0, q0, #1
270 ; CHECK-NEXT: vext.32 q0, q1, q1, #1
277 ; CHECKBE-NEXT: vext.32 q8, q8, q8, #1
279 ; CHECKBE-NEXT: vext.32 q8, q9, q9, #1
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A D2012-07-10-shufnorm.ll6 …%vext = shufflevector <2 x double> zeroinitializer, <2 x double> undef, <8 x i32> <i32 0, i32 1, i…
7 …%vecinit = shufflevector <8 x double> %vext, <8 x double> undef, <8 x i32> <i32 0, i32 1, i32 unde…
H A D2012-1-10-buildvector.ll11 %vext.i = shufflevector <2 x i64> undef, <2 x i64> undef, <3 x i32> <i32 0, i32 1, i32 undef>
12 …%vecinit8.i = shufflevector <3 x i64> zeroinitializer, <3 x i64> %vext.i, <3 x i32> <i32 0, i32 3,…
/llvm-project-15.0.7/llvm/utils/PerfectShuffle/
H A DPerfectShuffle.cpp603 struct vext : public Operator { struct
604 vext(const char *Name, unsigned Opc) in vext() function
609 vext<1> the_vext1("vext1", OP_VEXT1);
610 vext<2> the_vext2("vext2", OP_VEXT2);
611 vext<3> the_vext3("vext3", OP_VEXT3);
/llvm-project-15.0.7/clang/test/CodeGenOpenCL/
H A Dpartial_initializer.cl54 …// CHECK: %[[vext:.*]] = shufflevector <2 x i32> %[[v6]], <2 x i32> poison, <4 x i32> <i32 0, i32 …
55 …// CHECK: %[[vecinit:.*]] = shufflevector <4 x i32> %[[vext]], <4 x i32> undef, <4 x i32> <i32 0, …
/llvm-project-15.0.7/llvm/test/Analysis/CostModel/PowerPC/
H A Dinsert_extract-inseltpoison.ll163 define void @vext(<8 x i16> %p1, <16 x i8> %p2) {
164 ; CHECK-P7-LABEL: 'vext'
169 ; CHECK-P8LE-LABEL: 'vext'
174 ; CHECK-P9BE-LABEL: 'vext'
179 ; CHECK-P9LE-LABEL: 'vext'
H A Dinsert_extract.ll163 define void @vext(<8 x i16> %p1, <16 x i8> %p2) {
164 ; CHECK-P7-LABEL: 'vext'
169 ; CHECK-P8LE-LABEL: 'vext'
174 ; CHECK-P9BE-LABEL: 'vext'
179 ; CHECK-P9LE-LABEL: 'vext'
/llvm-project-15.0.7/llvm/test/MC/Disassembler/ARM/
H A Dneon-tests.txt93 # CHECK: vext.32 q4, q2, q1, #1
H A Dneont2.txt1284 # CHECK: vext.8 d16, d17, d16, #3
1286 # CHECK: vext.8 d16, d17, d16, #5
1288 # CHECK: vext.8 q8, q9, q8, #3
1290 # CHECK: vext.8 q8, q9, q8, #7
1292 # CHECK: vext.16 d16, d17, d16, #3
1294 # CHECK: vext.32 q8, q9, q8, #3
1330 # CHECK: vext.8 d16, d17, d16, #3
1332 # CHECK: vext.8 d16, d17, d16, #5
1334 # CHECK: vext.8 q8, q9, q8, #3
1336 # CHECK: vext.8 q8, q9, q8, #7
[all …]
/llvm-project-15.0.7/llvm/test/tools/llvm-mca/ARM/
H A Dcortex-a57-neon-instructions.s702 vext.8 d16, d17, d16, #3
703 vext.8 d16, d17, d16, #5
704 vext.8 q8, q9, q8, #3
705 vext.8 q8, q9, q8, #7
706 vext.16 d16, d17, d16, #3
707 vext.32 q8, q9, q8, #3
1818 # CHECK-NEXT: 1 3 0.50 vext.8 d16, d17, d16, #3
1819 # CHECK-NEXT: 1 3 0.50 vext.8 d16, d17, d16, #5
1820 # CHECK-NEXT: 1 3 0.50 vext.8 q8, q9, q8, #3
1821 # CHECK-NEXT: 1 3 0.50 vext.8 q8, q9, q8, #7
[all …]

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