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/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dextract-vector-elt-build-vector-combine.ll30 store <4 x i32> %vec3, <4 x i32> addrspace(1)* %out0
31 store <4 x i32> %vec3, <4 x i32> addrspace(1)* %out1
33 %extract0 = extractelement <4 x i32> %vec3, i32 0
34 %extract1 = extractelement <4 x i32> %vec3, i32 1
35 %extract2 = extractelement <4 x i32> %vec3, i32 2
36 %extract3 = extractelement <4 x i32> %vec3, i32 3
72 %extract0 = extractelement <4 x i32> %vec3, i32 0
73 %extract1 = extractelement <4 x i32> %vec3, i32 1
74 %extract2 = extractelement <4 x i32> %vec3, i32 2
75 %extract3 = extractelement <4 x i32> %vec3, i32 3
[all …]
H A Doperand-folding.ll74 %vec3 = insertelement <4 x i32> %vec2, i32 %tmp3, i32 3
75 %tmp4 = xor <4 x i32> <i32 5, i32 5, i32 5, i32 5>, %vec3
106 %vec3 = insertelement <4 x i32> %vec2, i32 %tmp3, i32 3
107 %tmp4 = xor <4 x i32> <i32 100, i32 100, i32 100, i32 100>, %vec3
H A Dcube.ll24 %vec3 = insertelement <4 x float> %vec2, float %cubema, i32 3
25 store <4 x float> %vec3, <4 x float> addrspace(1)* %out
/llvm-project-15.0.7/llvm/test/Transforms/InstSimplify/ConstProp/
H A DInsertElement-inseltpoison.ll21 %vec3 = insertelement <4 x i64> %vec2, i64 -3, i32 2
22 %vec4 = insertelement <4 x i64> %vec3, i64 -4, i32 3
32 %vec3 = insertelement <4 x i64> %vec2, i64 -3, i32 2
33 %vec4 = insertelement <4 x i64> %vec3, i64 -4, i32 3
34 %vec5 = insertelement <4 x i64> %vec3, i64 -5, i32 4
H A DInsertElement.ll21 %vec3 = insertelement <4 x i64> %vec2, i64 -3, i32 2
22 %vec4 = insertelement <4 x i64> %vec3, i64 -4, i32 3
32 %vec3 = insertelement <4 x i64> %vec2, i64 -3, i32 2
33 %vec4 = insertelement <4 x i64> %vec3, i64 -4, i32 3
34 %vec5 = insertelement <4 x i64> %vec3, i64 -5, i32 4
/llvm-project-15.0.7/clang/test/CodeGen/
H A Dinit.c46 typedef union vec3 { union
49 } vec3; typedef
50 vec3 f5(vec3 value) { in f5()
51 return (vec3) {{ in f5()
/llvm-project-15.0.7/llvm/test/CodeGen/X86/avx512-shuffles/
H A Dshuffle-interleave.ll22 %res = select <4 x i1> %cmp, <4 x float> %shuf, <4 x float> %vec3
48 %res = select <4 x i1> %cmp, <4 x float> %shuf, <4 x float> %vec3
74 %res = select <4 x i1> %cmp, <4 x float> %shuf, <4 x float> %vec3
108 %res = select <4 x i1> %cmp, <4 x float> %shuf, <4 x float> %vec3
144 %res = select <4 x i1> %cmp, <4 x float> %shuf, <4 x float> %vec3
173 %res = select <4 x i1> %cmp, <4 x float> %shuf, <4 x float> %vec3
202 %res = select <4 x i1> %cmp, <4 x float> %shuf, <4 x float> %vec3
240 %res = select <4 x i1> %cmp, <4 x float> %shuf, <4 x float> %vec3
276 %res = select <8 x i1> %cmp, <8 x float> %shuf, <8 x float> %vec3
302 %res = select <8 x i1> %cmp, <8 x float> %shuf, <8 x float> %vec3
[all …]
H A Dshuffle-vec.ll24 %res = select <8 x i1> %cmp, <8 x float> %shuf, <8 x float> %vec3
50 %res = select <8 x i1> %cmp, <8 x float> %shuf, <8 x float> %vec3
76 %res = select <8 x i1> %cmp, <8 x float> %shuf, <8 x float> %vec3
110 %res = select <8 x i1> %cmp, <8 x float> %shuf, <8 x float> %vec3
1039 %res = select <8 x i1> %cmp, <8 x i32> %shuf, <8 x i32> %vec3
1063 %res = select <8 x i1> %cmp, <8 x i32> %shuf, <8 x i32> %vec3
1087 %res = select <8 x i1> %cmp, <8 x i32> %shuf, <8 x i32> %vec3
1119 %res = select <8 x i1> %cmp, <8 x i32> %shuf, <8 x i32> %vec3
1153 %res = select <8 x i1> %cmp, <8 x i32> %shuf, <8 x i32> %vec3
1180 %res = select <8 x i1> %cmp, <8 x i32> %shuf, <8 x i32> %vec3
[all …]
H A Dunpack.ll22 %res = select <4 x i1> %cmp, <4 x float> %shuf, <4 x float> %vec3
48 %res = select <4 x i1> %cmp, <4 x float> %shuf, <4 x float> %vec3
74 %res = select <4 x i1> %cmp, <4 x float> %shuf, <4 x float> %vec3
108 %res = select <4 x i1> %cmp, <4 x float> %shuf, <4 x float> %vec3
144 %res = select <4 x i1> %cmp, <4 x float> %shuf, <4 x float> %vec3
173 %res = select <4 x i1> %cmp, <4 x float> %shuf, <4 x float> %vec3
202 %res = select <4 x i1> %cmp, <4 x float> %shuf, <4 x float> %vec3
240 %res = select <4 x i1> %cmp, <4 x float> %shuf, <4 x float> %vec3
276 %res = select <8 x i1> %cmp, <8 x float> %shuf, <8 x float> %vec3
302 %res = select <8 x i1> %cmp, <8 x float> %shuf, <8 x float> %vec3
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/Inline/
H A Dinline-byval-bonus.ll12 %struct.sphere = type { %struct.vec3, double, %struct.material, %struct.sphere* }
13 %struct.vec3 = type { double, double, double }
14 %struct.material = type { %struct.vec3, double, double }
15 %struct.ray = type { %struct.vec3, %struct.vec3 }
16 %struct.spoint = type { %struct.vec3, %struct.vec3, %struct.vec3, double }
/llvm-project-15.0.7/clang/test/Sema/
H A Dext_vector_components.c12 float3 vec3; in test() local
25 vec3 = vec4.xyz; // legal, shorten in test()
51 vec3 = vec4.rgb; // legal, shorten in test()
H A Dext_vector_casts.c17 float3 vec3; in test() local
25 vec3 += vec2; // expected-error {{cannot convert between vector values of different size}} in test()
26 vec4 += vec3; // expected-error {{cannot convert between vector values of different size}} in test()
/llvm-project-15.0.7/llvm/test/Transforms/SLPVectorizer/X86/
H A Dc-ray.ll6 %struct.ray = type { %struct.vec3, %struct.vec3 }
7 %struct.vec3 = type { double, double, double }
8 %struct.sphere = type { %struct.vec3, double, %struct.material, ptr }
9 %struct.material = type { %struct.vec3, double, double }
108 %y19 = getelementptr inbounds %struct.vec3, ptr %ray, i64 0, i32 1
110 %y21 = getelementptr inbounds %struct.vec3, ptr %sph, i64 0, i32 1
116 %z28 = getelementptr inbounds %struct.vec3, ptr %ray, i64 0, i32 2
118 %z30 = getelementptr inbounds %struct.vec3, ptr %sph, i64 0, i32 2
H A Dinsert-shuffle.ll53 %vec3 = insertelement <2 x float> undef, float %add39, i32 0
54 %vec4 = insertelement <2 x float> %vec3, float %add54, i32 1
/llvm-project-15.0.7/llvm/test/CodeGen/SPARC/
H A Dvector-extract-elt.ll12 %vec3 = lshr <4 x i16> %vec2, <i16 2, i16 2, i16 2, i16 2>
13 %vec4 = sext <4 x i16> %vec3 to <4 x i32>
/llvm-project-15.0.7/clang/test/CodeGenOpenCL/
H A DvectorLoadStore.cl8 // Check for optimized vec3 load/store which treats vec3 as vec4.
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dvldm-liveness.ll23 %vec3 = insertelement <4 x float> %vec2, float %val4, i32 2
24 %vec4 = insertelement <4 x float> %vec3, float %val2, i32 3
H A DlowerMUL-newload.ll151 %vec3 = add <4 x i32> %1, %0
152 %2 = trunc <4 x i32> %vec3 to <4 x i16>
159 %vec5 = mul <4 x i32> %3, %vec3
226 %vec3 = add <4 x i32> %1, %0
227 %2 = trunc <4 x i32> %vec3 to <4 x i16>
234 %vec5 = mul <4 x i32> %3, %vec3
/llvm-project-15.0.7/llvm/test/CodeGen/Hexagon/vect/
H A Dvect-vsplatb.ll25 %vec3 = insertelement <4 x i8> %vec2, i8 %v, i32 3
26 %mulp_vec = mul <4 x i8> %_p_vec_full, %vec3
/llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/
H A Dvec-perm-12.ll40 %vec3 = insertelement <4 x i32> %vec2, i32 %elt3, i32 3
41 ret <4 x i32> %vec3
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dmisched-stp.ll25 %vec3 = insertelement <4 x i32> %vec2, i32 %val, i32 3
27 store <4 x i32> %vec3, <4 x i32>* %3, align 4
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dvector-interleaved-load-i64-stride-6.ll11 …e6_vf2(ptr %in.vec, ptr %out.vec0, ptr %out.vec1, ptr %out.vec2, ptr %out.vec3, ptr %out.vec4, ptr…
88 %strided.vec3 = shufflevector <12 x i64> %wide.vec, <12 x i64> poison, <2 x i32> <i32 3, i32 9>
95 store <2 x i64> %strided.vec3, ptr %out.vec3, align 32
102 …e6_vf4(ptr %in.vec, ptr %out.vec0, ptr %out.vec1, ptr %out.vec2, ptr %out.vec3, ptr %out.vec4, ptr…
283 …%strided.vec3 = shufflevector <24 x i64> %wide.vec, <24 x i64> poison, <4 x i32> <i32 3, i32 9, i3…
290 store <4 x i64> %strided.vec3, ptr %out.vec3, align 32
297 …e6_vf8(ptr %in.vec, ptr %out.vec0, ptr %out.vec1, ptr %out.vec2, ptr %out.vec3, ptr %out.vec4, ptr…
668 …%strided.vec3 = shufflevector <48 x i64> %wide.vec, <48 x i64> poison, <8 x i32> <i32 3, i32 9, i3…
675 store <8 x i64> %strided.vec3, ptr %out.vec3, align 32
H A Dvector-interleaved-load-i64-stride-4.ll11 …i64_stride4_vf2(ptr %in.vec, ptr %out.vec0, ptr %out.vec1, ptr %out.vec2, ptr %out.vec3) nounwind {
84 %strided.vec3 = shufflevector <8 x i64> %wide.vec, <8 x i64> poison, <2 x i32> <i32 3, i32 7>
89 store <2 x i64> %strided.vec3, ptr %out.vec3, align 32
94 …i64_stride4_vf4(ptr %in.vec, ptr %out.vec0, ptr %out.vec1, ptr %out.vec2, ptr %out.vec3) nounwind {
192 …%strided.vec3 = shufflevector <16 x i64> %wide.vec, <16 x i64> poison, <4 x i32> <i32 3, i32 7, i3…
197 store <4 x i64> %strided.vec3, ptr %out.vec3, align 32
202 …i64_stride4_vf8(ptr %in.vec, ptr %out.vec0, ptr %out.vec1, ptr %out.vec2, ptr %out.vec3) nounwind {
423 …%strided.vec3 = shufflevector <32 x i64> %wide.vec, <32 x i64> poison, <8 x i32> <i32 3, i32 7, i3…
428 store <8 x i64> %strided.vec3, ptr %out.vec3, align 32
433 …64_stride4_vf16(ptr %in.vec, ptr %out.vec0, ptr %out.vec1, ptr %out.vec2, ptr %out.vec3) nounwind {
[all …]
H A Dvector-interleaved-load-i8-stride-4.ll11 …_i8_stride4_vf2(ptr %in.vec, ptr %out.vec0, ptr %out.vec1, ptr %out.vec2, ptr %out.vec3) nounwind {
70 %strided.vec3 = shufflevector <8 x i8> %wide.vec, <8 x i8> poison, <2 x i32> <i32 3, i32 7>
75 store <2 x i8> %strided.vec3, ptr %out.vec3, align 32
80 …_i8_stride4_vf4(ptr %in.vec, ptr %out.vec0, ptr %out.vec1, ptr %out.vec2, ptr %out.vec3) nounwind {
145 …%strided.vec3 = shufflevector <16 x i8> %wide.vec, <16 x i8> poison, <4 x i32> <i32 3, i32 7, i32 …
150 store <4 x i8> %strided.vec3, ptr %out.vec3, align 32
155 …_i8_stride4_vf8(ptr %in.vec, ptr %out.vec0, ptr %out.vec1, ptr %out.vec2, ptr %out.vec3) nounwind {
277 store <8 x i8> %strided.vec3, ptr %out.vec3, align 32
282 …i8_stride4_vf16(ptr %in.vec, ptr %out.vec0, ptr %out.vec1, ptr %out.vec2, ptr %out.vec3) nounwind {
541 store <16 x i8> %strided.vec3, ptr %out.vec3, align 32
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A Daix-cc-ext-vec-abi.ll9 define dso_local <4 x i32> @vec_callee(<4 x i32> %vec1, <4 x i32> %vec2, <4 x i32> %vec3, <4 x i32>…
12 %add1 = add <4 x i32> %add, %vec3

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