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/llvm-project-15.0.7/llvm/test/Instrumentation/MemorySanitizer/
H A Dwith-call-type-size.ll8 %vec1 = insertelement <4 x i32> %vec, i32 %x, i1 %idx
9 ret <4 x i32> %vec1
17 %vec1 = insertelement <4 x i32> %vec, i32 %x, i2 %idx
18 ret <4 x i32> %vec1
27 ret <4 x i32> %vec1
36 ret <4 x i32> %vec1
45 ret <4 x i32> %vec1
53 ret <4 x i32> %vec1
62 ret <4 x i32> %vec1
71 ret <4 x i32> %vec1
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/X86/avx512-shuffles/
H A Dshuffle-interleave.ll4 define <4 x float> @test_4xfloat_shuff_mask0(<4 x float> %vec1, <4 x float> %vec2) {
90 define <4 x float> @test_4xfloat_shuff_mask3(<4 x float> %vec1, <4 x float> %vec2) {
124 define <4 x float> @test_4xfloat_shuff_mem_mask0(<4 x float> %vec1, ptr %vec2p) {
220 define <4 x float> @test_4xfloat_shuff_mem_mask3(<4 x float> %vec1, ptr %vec2p) {
258 define <8 x float> @test_8xfloat_shuff_mask0(<8 x float> %vec1, <8 x float> %vec2) {
344 define <8 x float> @test_8xfloat_shuff_mask3(<8 x float> %vec1, <8 x float> %vec2) {
378 define <8 x float> @test_8xfloat_shuff_mem_mask0(<8 x float> %vec1, ptr %vec2p) {
474 define <8 x float> @test_8xfloat_shuff_mem_mask3(<8 x float> %vec1, ptr %vec2p) {
632 define <16 x float> @test_16xfloat_shuff_mem_mask0(<16 x float> %vec1, ptr %vec2p) {
728 define <16 x float> @test_16xfloat_shuff_mem_mask3(<16 x float> %vec1, ptr %vec2p) {
[all …]
H A Dshuffle-vec.ll6 define <8 x float> @test_8xfloat_shuff_mask0(<8 x float> %vec1, <8 x float> %vec2) {
1022 define <8 x i32> @test_8xi32_shuff_mask0(<8 x i32> %vec1, <8 x i32> %vec2) {
1102 define <8 x i32> @test_8xi32_shuff_mask3(<8 x i32> %vec1, <8 x i32> %vec2) {
1134 define <8 x i32> @test_8xi32_shuff_mem_mask0(<8 x i32> %vec1, ptr %vec2p) {
1224 define <8 x i32> @test_8xi32_shuff_mem_mask3(<8 x i32> %vec1, ptr %vec2p) {
1498 define <4 x i64> @test_4xi64_shuff_mask0(<4 x i64> %vec1, <4 x i64> %vec2) {
1578 define <4 x i64> @test_4xi64_shuff_mask3(<4 x i64> %vec1, <4 x i64> %vec2) {
1610 define <4 x i64> @test_4xi64_shuff_mem_mask0(<4 x i64> %vec1, ptr %vec2p) {
1700 define <4 x i64> @test_4xi64_shuff_mem_mask3(<4 x i64> %vec1, ptr %vec2p) {
1848 define <8 x i64> @test_8xi64_shuff_mem_mask0(<8 x i64> %vec1, ptr %vec2p) {
[all …]
H A Dunpack.ll4 define <4 x float> @test_4xfloat_unpack_low_mask0(<4 x float> %vec1, <4 x float> %vec2) {
9 %res = shufflevector <4 x float> %vec1, <4 x float> %vec2, <4 x i32> <i32 0, i32 4, i32 1, i32 5>
90 define <4 x float> @test_4xfloat_unpack_low_mask3(<4 x float> %vec1, <4 x float> %vec2) {
124 define <4 x float> @test_4xfloat_unpack_low_mem_mask0(<4 x float> %vec1, ptr %vec2p) {
220 define <4 x float> @test_4xfloat_unpack_low_mem_mask3(<4 x float> %vec1, ptr %vec2p) {
258 define <8 x float> @test_8xfloat_unpack_low_mask0(<8 x float> %vec1, <8 x float> %vec2) {
344 define <8 x float> @test_8xfloat_unpack_low_mask3(<8 x float> %vec1, <8 x float> %vec2) {
378 define <8 x float> @test_8xfloat_unpack_low_mem_mask0(<8 x float> %vec1, ptr %vec2p) {
474 define <8 x float> @test_8xfloat_unpack_low_mem_mask3(<8 x float> %vec1, ptr %vec2p) {
771 %res = shufflevector <2 x double> %vec1, <2 x double> %vec2, <2 x i32> <i32 0, i32 2>
[all …]
/llvm-project-15.0.7/polly/lib/External/isl/
H A Disl_vec.c170 if (!vec1 || !vec2) in isl_vec_concat()
175 return vec1; in isl_vec_concat()
183 vec1 = isl_vec_extend(vec1, vec1->size + vec2->size); in isl_vec_concat()
184 if (!vec1) in isl_vec_concat()
190 return vec1; in isl_vec_concat()
348 return isl_bool_ok(isl_seq_eq(vec1->el, vec2->el, vec1->size)); in isl_vec_is_equal()
499 vec1 = isl_vec_cow(vec1); in isl_vec_add()
503 isl_assert(vec1->ctx, vec1->size == vec2->size, goto error); in isl_vec_add()
505 isl_seq_combine(vec1->el, vec1->ctx->one, vec1->el, in isl_vec_add()
506 vec1->ctx->one, vec2->el, vec1->size); in isl_vec_add()
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/GlobalISel/
H A Dlegalize-min-max.mir19 %vec1:_(<8 x s8>) = G_IMPLICIT_DEF
20 %smin:_(<8 x s8>) = G_SMIN %vec, %vec1
40 %vec1:_(<16 x s8>) = G_IMPLICIT_DEF
41 %smin:_(<16 x s8>) = G_SMIN %vec, %vec1
68 %vec1:_(<32 x s8>) = G_IMPLICIT_DEF
89 %vec1:_(<4 x s16>) = G_IMPLICIT_DEF
110 %vec1:_(<8 x s16>) = G_IMPLICIT_DEF
159 %vec1:_(<2 x s32>) = G_IMPLICIT_DEF
180 %vec1:_(<4 x s32>) = G_IMPLICIT_DEF
208 %vec1:_(<8 x s32>) = G_IMPLICIT_DEF
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Darm64-copy-tuple.ll18 %vec1 = extractvalue { <8 x i8>, <8 x i8> } %vec, 1
20 tail call void @llvm.aarch64.neon.st2.v8i8.p0i8(<8 x i8> %vec0, <8 x i8> %vec1, i8* %addr)
23 tail call void @llvm.aarch64.neon.st2.v8i8.p0i8(<8 x i8> %vec0, <8 x i8> %vec1, i8* %addr)
35 %vec1 = extractvalue { <8 x i8>, <8 x i8> } %vec, 1
37 tail call void @llvm.aarch64.neon.st2.v8i8.p0i8(<8 x i8> %vec0, <8 x i8> %vec1, i8* %addr)
40 tail call void @llvm.aarch64.neon.st2.v8i8.p0i8(<8 x i8> %vec0, <8 x i8> %vec1, i8* %addr)
52 %vec1 = extractvalue { <8 x i8>, <8 x i8> } %vec, 1
69 %vec1 = extractvalue { <8 x i8>, <8 x i8> } %vec, 1
87 %vec1 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8> } %vec, 1
107 %vec1 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8> } %vec, 1
[all …]
H A DlowerMUL-newload.ll13 %v1 = sext <4 x i16> %vec1 to <4 x i32>
31 %v1 = sext <4 x i16> %vec1 to <4 x i32>
58 %v1 = sext <4 x i16> %vec1 to <4 x i32>
81 %v1 = sext <4 x i16> %vec1 to <4 x i32>
99 %v1 = sext <4 x i16> %vec1 to <4 x i32>
126 %v1 = sext <4 x i16> %vec1 to <4 x i32>
149 %v1 = sext <2 x i32> %vec1 to <2 x i64>
167 %v1 = sext <2 x i32> %vec1 to <2 x i64>
194 %v1 = sext <2 x i32> %vec1 to <2 x i64>
217 %v1 = sext <2 x i32> %vec1 to <2 x i64>
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dpacked-op-sel.ll19 %vec1 = load volatile <2 x half>, <2 x half> addrspace(3)* %lds.gep1, align 4
47 %vec1 = load volatile <2 x half>, <2 x half> addrspace(3)* %lds.gep1, align 4
76 %vec1 = load volatile <2 x half>, <2 x half> addrspace(3)* %lds.gep1, align 4
105 %vec1 = load volatile <2 x half>, <2 x half> addrspace(3)* %lds.gep1, align 4
135 %vec1 = load volatile <2 x half>, <2 x half> addrspace(3)* %lds.gep1, align 4
163 %vec1 = load volatile <2 x half>, <2 x half> addrspace(3)* %lds.gep1, align 4
218 %vec1 = load volatile <2 x half>, <2 x half> addrspace(3)* %lds.gep1, align 4
246 %vec1 = load volatile <2 x half>, <2 x half> addrspace(3)* %lds.gep1, align 4
332 %vec1 = load volatile <2 x i16>, <2 x i16> addrspace(3)* %lds.gep1, align 4
334 %vec1.elt1.broadcast = shufflevector <2 x i16> %vec1, <2 x i16> undef, <2 x i32> <i32 1, i32 1>
[all …]
H A Dbitcast-vector-extract.ll18 …%vec1.bc = bitcast <8 x i32> <i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 9> to <8 x floa…
19 store volatile <8 x float> %vec1.bc, <8 x float> addrspace(1)* %out
34 %vec1.bc = bitcast <4 x i64> <i64 7, i64 7, i64 7, i64 9> to <8 x float>
35 store volatile <8 x float> %vec1.bc, <8 x float> addrspace(1)* %out
50 %vec1.bc = bitcast <4 x i64> <i64 7, i64 7, i64 7, i64 9> to <4 x double>
51 store volatile <4 x double> %vec1.bc, <4 x double> addrspace(1)* %out
66 …%vec1.bc = bitcast <16 x i16> <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 …
67 store volatile <8 x float> %vec1.bc, <8 x float> addrspace(1)* %out
H A Dextract-vector-elt-build-vector-combine.ll26 %vec1 = insertelement <4 x i32> %vec0, i32 %elt1, i32 1
27 %vec2 = insertelement <4 x i32> %vec1, i32 %elt2, i32 2
68 %vec1 = insertelement <4 x i32> %vec0, i32 %elt1, i32 1
69 %vec2 = insertelement <4 x i32> %vec1, i32 %elt2, i32 2
112 %vec1 = insertelement <4 x i32> %vec0, i32 %elt1, i32 1
113 %vec2 = insertelement <4 x i32> %vec1, i32 %elt2, i32 2
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dvector-interleaved-load-i8-stride-2.ll11 define void @load_i8_stride2_vf2(ptr %in.vec, ptr %out.vec0, ptr %out.vec1) nounwind {
46 %strided.vec1 = shufflevector <4 x i8> %wide.vec, <4 x i8> poison, <2 x i32> <i32 1, i32 3>
49 store <2 x i8> %strided.vec1, ptr %out.vec1, align 32
54 define void @load_i8_stride2_vf4(ptr %in.vec, ptr %out.vec0, ptr %out.vec1) nounwind {
90 store <4 x i8> %strided.vec1, ptr %out.vec1, align 32
95 define void @load_i8_stride2_vf8(ptr %in.vec, ptr %out.vec0, ptr %out.vec1) nounwind {
130 store <8 x i8> %strided.vec1, ptr %out.vec1, align 32
135 define void @load_i8_stride2_vf16(ptr %in.vec, ptr %out.vec0, ptr %out.vec1) nounwind {
187 store <16 x i8> %strided.vec1, ptr %out.vec1, align 32
192 define void @load_i8_stride2_vf32(ptr %in.vec, ptr %out.vec0, ptr %out.vec1) nounwind {
[all …]
H A D2011-04-19-sclr-bb.ll12 %vec1 = phi <4 x i1> [ %vec1_or_2, %LOOP ], [ zeroinitializer, %ENTRY ]
14 %vec1_or_2 = or <4 x i1> %vec1, %vec2
15 %vec2_and_1 = and <4 x i1> %vec2, %vec1
H A Dvector-interleaved-load-i32-stride-2.ll11 define void @load_i32_stride2_vf2(ptr %in.vec, ptr %out.vec0, ptr %out.vec1) nounwind {
41 %strided.vec1 = shufflevector <4 x i32> %wide.vec, <4 x i32> poison, <2 x i32> <i32 1, i32 3>
44 store <2 x i32> %strided.vec1, ptr %out.vec1, align 32
49 define void @load_i32_stride2_vf4(ptr %in.vec, ptr %out.vec0, ptr %out.vec1) nounwind {
86 store <4 x i32> %strided.vec1, ptr %out.vec1, align 32
91 define void @load_i32_stride2_vf8(ptr %in.vec, ptr %out.vec0, ptr %out.vec1) nounwind {
151 store <8 x i32> %strided.vec1, ptr %out.vec1, align 32
156 define void @load_i32_stride2_vf16(ptr %in.vec, ptr %out.vec0, ptr %out.vec1) nounwind {
247 store <16 x i32> %strided.vec1, ptr %out.vec1, align 32
252 define void @load_i32_stride2_vf32(ptr %in.vec, ptr %out.vec0, ptr %out.vec1) nounwind {
[all …]
H A Dscalar_sse_minmax.ll24 %vec1 = insertelement <4 x float> undef, float %y, i32 0
25 %retval = tail call <4 x float> @llvm.x86.sse.min.ss(<4 x float> %vec0, <4 x float> %vec1)
50 %vec1 = insertelement <4 x float> undef, float %y, i32 0
51 %retval = tail call <4 x float> @llvm.x86.sse.max.ss(<4 x float> %vec0, <4 x float> %vec1)
H A Dvector-interleaved-load-i16-stride-2.ll11 define void @vf2(ptr %in.vec, ptr %out.vec0, ptr %out.vec1) nounwind {
41 %strided.vec1 = shufflevector <4 x i16> %wide.vec, <4 x i16> poison, <2 x i32> <i32 1, i32 3>
44 store <2 x i16> %strided.vec1, ptr %out.vec1, align 32
49 define void @vf4(ptr %in.vec, ptr %out.vec0, ptr %out.vec1) nounwind {
87 store <4 x i16> %strided.vec1, ptr %out.vec1, align 32
92 define void @vf8(ptr %in.vec, ptr %out.vec0, ptr %out.vec1) nounwind {
142 store <8 x i16> %strided.vec1, ptr %out.vec1, align 32
147 define void @vf16(ptr %in.vec, ptr %out.vec0, ptr %out.vec1) nounwind {
258 store <16 x i16> %strided.vec1, ptr %out.vec1, align 32
263 define void @vf32(ptr %in.vec, ptr %out.vec0, ptr %out.vec1) nounwind {
[all …]
/llvm-project-15.0.7/clang/test/CodeGen/
H A Darithmetic-fence-builtin.c24 __v2f32 vec1, vec2; in addit() local
25 vec1 = __arithmetic_fence(vec2); in addit()
27 vec2 = (vec2 + vec1); in addit()
H A Daarch64-sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS.c77 typedef int8_t vec1 __attribute__((vector_size(N / 8))); typedef
78 void f3(vec1);
H A Daarch64-sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS.cpp64 typedef int16_t vec1 __attribute__((vector_size(N / 8))); typedef
65 void f(vec1);
/llvm-project-15.0.7/llvm/test/Transforms/InstSimplify/ConstProp/
H A DInsertElement-inseltpoison.ll19 %vec1 = insertelement <4 x i64> poison, i64 -1, i32 0
20 %vec2 = insertelement <4 x i64> %vec1, i64 -2, i32 1
30 %vec1 = insertelement <4 x i64> poison, i64 -1, i32 0
31 %vec2 = insertelement <4 x i64> %vec1, i64 -2, i32 1
H A DInsertElement.ll19 %vec1 = insertelement <4 x i64> undef, i64 -1, i32 0
20 %vec2 = insertelement <4 x i64> %vec1, i64 -2, i32 1
30 %vec1 = insertelement <4 x i64> undef, i64 -1, i32 0
31 %vec2 = insertelement <4 x i64> %vec1, i64 -2, i32 1
/llvm-project-15.0.7/polly/lib/External/isl/include/isl/
H A Dvec.h40 isl_bool isl_vec_is_equal(__isl_keep isl_vec *vec1, __isl_keep isl_vec *vec2);
41 int isl_vec_cmp_element(__isl_keep isl_vec *vec1, __isl_keep isl_vec *vec2,
55 __isl_give isl_vec *isl_vec_add(__isl_take isl_vec *vec1,
59 __isl_give isl_vec *isl_vec_concat(__isl_take isl_vec *vec1,
/llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/
H A Dvec-move-13.ll12 %vec1 = insertelement <16 x i8> zeroinitializer, i8 %val1, i32 2
13 %vec2 = insertelement <16 x i8> %vec1, i8 %val2, i32 12
24 %vec1 = insertelement <8 x i16> zeroinitializer, i16 %val1, i32 3
25 %vec2 = insertelement <8 x i16> %vec1, i16 %val2, i32 5
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A DlowerMUL-newload.ll4 define arm_aapcs_vfpcc <4 x i16> @mla_args(<4 x i16> %vec0, <4 x i16> %vec1, <4 x i16> %vec2) {
13 %v1 = sext <4 x i16> %vec1 to <4 x i32>
39 %vec1 = load <4 x i16>, <4 x i16>* %vector_ptr1, align 8
40 %v1 = sext <4 x i16> %vec1 to <4 x i32>
63 %v1 = sext <4 x i16> %vec1 to <4 x i32>
89 %vec1 = load <4 x i16>, <4 x i16>* %vector_ptr1, align 8
90 %v1 = sext <4 x i16> %vec1 to <4 x i32>
145 %vec1 = load <4 x i16>, <4 x i16>* %vector_ptr1, align 8
146 %0 = zext <4 x i16> %vec1 to <4 x i32>
220 %vec1 = load <4 x i16>, <4 x i16>* %vector_ptr1, align 8
[all …]
/llvm-project-15.0.7/clang/test/Sema/
H A Darithmetic-fence-builtin.c28 __v4hi vec1, vec2; in addit() local
29 vec1 = __arithmetic_fence(vec2); in addit()

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