| /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/ |
| H A D | llvm.amdgcn.tbuffer.load.ll | 16 %vdata.f = bitcast <4 x i32> %vdata to <4 x float>
31 %vdata.f = bitcast <4 x i32> %vdata to <4 x float>
32 ret <4 x float> %vdata.f
44 %vdata.f = bitcast <4 x i32> %vdata to <4 x float>
58 %vdata.f = bitcast <4 x i32> %vdata to <4 x float>
67 %vdata.f = bitcast <4 x i32> %vdata to <4 x float>
76 %vdata.f = bitcast <4 x i32> %vdata to <4 x float>
85 %vdata.f = bitcast <4 x i32> %vdata to <4 x float>
94 %vdata.f = bitcast <2 x i32> %vdata to <2 x float>
102 %vdata.f = bitcast i32 %vdata to float
[all …]
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| H A D | llvm.amdgcn.struct.tbuffer.load.ll | 27 %vdata.f = bitcast <4 x i32> %vdata to <4 x float>
45 %vdata.f = bitcast <4 x i32> %vdata to <4 x float>
46 ret <4 x float> %vdata.f
65 %vdata.f = bitcast <4 x i32> %vdata to <4 x float>
81 %vdata.f = bitcast <4 x i32> %vdata to <4 x float>
92 %vdata.f = bitcast <4 x i32> %vdata to <4 x float>
104 %vdata.f = bitcast <4 x i32> %vdata to <4 x float>
115 %vdata.f = bitcast <4 x i32> %vdata to <4 x float>
126 %vdata.f = bitcast <2 x i32> %vdata to <2 x float>
136 %vdata.f = bitcast i32 %vdata to float
[all …]
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| H A D | llvm.amdgcn.raw.tbuffer.load.ll | 26 %vdata.f = bitcast <4 x i32> %vdata to <4 x float>
43 %vdata.f = bitcast <4 x i32> %vdata to <4 x float>
44 ret <4 x float> %vdata.f
62 %vdata.f = bitcast <4 x i32> %vdata to <4 x float>
78 %vdata.f = bitcast <4 x i32> %vdata to <4 x float>
79 ret <4 x float> %vdata.f
89 %vdata.f = bitcast <4 x i32> %vdata to <4 x float>
90 ret <4 x float> %vdata.f
99 %vdata.f = bitcast <2 x i32> %vdata to <2 x float>
109 %vdata.f = bitcast i32 %vdata to float
[all …]
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| H A D | llvm.amdgcn.tbuffer.load.dwordx3.ll | 9 …%vdata = call <3 x i32> @llvm.amdgcn.raw.tbuffer.load.v3i32(<4 x i32> %0, i32 42, i32 0, i32 78,…
10 %vdata.f = bitcast <3 x i32> %vdata to <3 x float>
11 ret <3 x float> %vdata.f
21 …%vdata = call <3 x i32> @llvm.amdgcn.struct.tbuffer.load.v3i32(<4 x i32> %0, i32 0, i32 42, i32 …
22 %vdata.f = bitcast <3 x i32> %vdata to <3 x float>
23 ret <3 x float> %vdata.f
32 …%vdata = call <3 x i32> @llvm.amdgcn.tbuffer.load.v3i32(<4 x i32> %0, i32 0, i32 0, i32 0, i32 4…
33 %vdata.f = bitcast <3 x i32> %vdata to <3 x float>
34 ret <3 x float> %vdata.f
|
| H A D | llvm.amdgcn.image.dim.gfx90a.ll | 113 define amdgpu_ps void @store_1d(<8 x i32> inreg %rsrc, <4 x float> %vdata, i32 %s) {
121 define amdgpu_ps void @store_2d(<8 x i32> inreg %rsrc, <4 x float> %vdata, i32 %s, i32 %t) {
129 define amdgpu_ps void @store_3d(<8 x i32> inreg %rsrc, <4 x float> %vdata, i32 %s, i32 %t, i32 %r) {
137 define amdgpu_ps void @store_cube(<8 x i32> inreg %rsrc, <4 x float> %vdata, i32 %s, i32 %t, i32 %s…
145 define amdgpu_ps void @store_1darray(<8 x i32> inreg %rsrc, <4 x float> %vdata, i32 %s, i32 %slice)…
194 define amdgpu_ps void @store_1d_V1(<8 x i32> inreg %rsrc, float %vdata, i32 %s) {
196 …call void @llvm.amdgcn.image.store.1d.f32.i32(float %vdata, i32 2, i32 %s, <8 x i32> %rsrc, i32 0,…
202 define amdgpu_ps void @store_1d_V2(<8 x i32> inreg %rsrc, <2 x float> %vdata, i32 %s) {
234 define amdgpu_ps void @store_1d_glc(<8 x i32> inreg %rsrc, <4 x float> %vdata, i32 %s) {
242 define amdgpu_ps void @store_1d_slc(<8 x i32> inreg %rsrc, <4 x float> %vdata, i32 %s) {
[all …]
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| H A D | llvm.amdgcn.tbuffer.store.ll | 32 define amdgpu_ps void @tbuffer_store_scalar_and_imm_offs(<4 x i32> inreg, <4 x float> %vdata, i32 i…
34 %in1 = bitcast <4 x float> %vdata to <4 x i32>
41 define amdgpu_ps void @buffer_store_idx(<4 x i32> inreg, <4 x float> %vdata, i32 %vindex) {
43 %in1 = bitcast <4 x float> %vdata to <4 x i32>
50 define amdgpu_ps void @buffer_store_ofs(<4 x i32> inreg, <4 x float> %vdata, i32 %voffset) {
52 %in1 = bitcast <4 x float> %vdata to <4 x i32>
59 define amdgpu_ps void @buffer_store_both(<4 x i32> inreg, <4 x float> %vdata, i32 %vindex, i32 %vof…
61 %in1 = bitcast <4 x float> %vdata to <4 x i32>
74 define amdgpu_ps void @buffer_store_wait(<4 x i32> inreg, <4 x float> %vdata, i32 %vindex.1, i32 %v…
76 %in1 = bitcast <4 x float> %vdata to <4 x i32>
|
| H A D | llvm.amdgcn.struct.tbuffer.store.ll | 49 define amdgpu_ps void @tbuffer_store_scalar_and_imm_offs(<4 x i32> inreg, <4 x float> %vdata, i32 i…
51 %in1 = bitcast <4 x float> %vdata to <4 x i32>
60 define amdgpu_ps void @buffer_store_idx(<4 x i32> inreg, <4 x float> %vdata, i32 %vindex) {
62 %in1 = bitcast <4 x float> %vdata to <4 x i32>
71 define amdgpu_ps void @buffer_store_ofs(<4 x i32> inreg, <4 x float> %vdata, i32 %voffset) {
73 %in1 = bitcast <4 x float> %vdata to <4 x i32>
82 define amdgpu_ps void @buffer_store_both(<4 x i32> inreg, <4 x float> %vdata, i32 %vindex, i32 %vof…
84 %in1 = bitcast <4 x float> %vdata to <4 x i32>
101 define amdgpu_ps void @buffer_store_wait(<4 x i32> inreg, <4 x float> %vdata, i32 %vindex.1, i32 %v…
103 %in1 = bitcast <4 x float> %vdata to <4 x i32>
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| H A D | llvm.amdgcn.image.a16.dim.ll | 285 define amdgpu_ps void @store_1d(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords) {
303 …call void @llvm.amdgcn.image.store.1d.v4f32.i16(<4 x float> %vdata, i32 15, i16 %s, <8 x i32> %rsr…
307 define amdgpu_ps void @store_2d(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords) {
378 define amdgpu_ps void @store_1darray(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords) {
474 define amdgpu_ps void @store_mip_1d(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords) {
800 define amdgpu_ps void @store_1d_V1(<8 x i32> inreg %rsrc, float %vdata, <2 x i16> %coords) {
818 …call void @llvm.amdgcn.image.store.1d.f32.i16(float %vdata, i32 2, i16 %s, <8 x i32> %rsrc, i32 0,…
822 define amdgpu_ps void @store_1d_V2(<8 x i32> inreg %rsrc, <2 x float> %vdata, <2 x i16> %coords) {
898 define amdgpu_ps void @store_1d_glc(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords) {
920 define amdgpu_ps void @store_1d_slc(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords) {
[all …]
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| H A D | llvm.amdgcn.raw.tbuffer.store.ll | 46 define amdgpu_ps void @tbuffer_store_scalar_and_imm_offs(<4 x i32> inreg, <4 x float> %vdata, i32 i…
48 %in1 = bitcast <4 x float> %vdata to <4 x i32>
57 define amdgpu_ps void @buffer_store_ofs(<4 x i32> inreg, <4 x float> %vdata, i32 %voffset) {
59 %in1 = bitcast <4 x float> %vdata to <4 x i32>
|
| H A D | llvm.amdgcn.image.a16.encode.ll | 369 define amdgpu_ps void @store_1d(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords) {
387 …call void @llvm.amdgcn.image.store.1d.v4f32.i16(<4 x float> %vdata, i32 15, i16 %s, <8 x i32> %rsr…
391 define amdgpu_ps void @store_2d(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords) {
462 define amdgpu_ps void @store_1darray(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords) {
558 define amdgpu_ps void @store_mip_1d(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords) {
944 define amdgpu_ps void @store_1d_V1(<8 x i32> inreg %rsrc, float %vdata, <2 x i16> %coords) {
962 …call void @llvm.amdgcn.image.store.1d.f32.i16(float %vdata, i32 2, i16 %s, <8 x i32> %rsrc, i32 0,…
966 define amdgpu_ps void @store_1d_V2(<8 x i32> inreg %rsrc, <2 x float> %vdata, <2 x i16> %coords) {
1060 define amdgpu_ps void @store_1d_glc(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords) {
1082 define amdgpu_ps void @store_1d_slc(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords) {
[all …]
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| /llvm-project-15.0.7/compiler-rt/lib/sanitizer_common/ |
| H A D | sanitizer_symbolizer_libbacktrace.cpp | 48 static void CplusV3DemangleCallback(const char *s, size_t l, void *vdata) { in CplusV3DemangleCallback() argument
49 CplusV3DemangleData *data = (CplusV3DemangleData *)vdata; in CplusV3DemangleCallback()
109 static int SymbolizeCodePCInfoCallback(void *vdata, uintptr_t addr, in SymbolizeCodePCInfoCallback() argument
112 SymbolizeCodeCallbackArg *cdata = (SymbolizeCodeCallbackArg *)vdata; in SymbolizeCodePCInfoCallback()
124 static void SymbolizeCodeCallback(void *vdata, uintptr_t addr, in SymbolizeCodeCallback() argument
126 SymbolizeCodeCallbackArg *cdata = (SymbolizeCodeCallbackArg *)vdata; in SymbolizeCodeCallback()
134 static void SymbolizeDataCallback(void *vdata, uintptr_t, const char *symname, in SymbolizeDataCallback() argument
136 DataInfo *info = (DataInfo *)vdata; in SymbolizeDataCallback()
|
| /llvm-project-15.0.7/libc/AOR_v20.02/string/aarch64/ |
| H A D | strchr-mte.S | 30 #define vdata v1 macro
73 cmeq vhas_nul.16b, vdata.16b, #0
74 cmeq vhas_chr.16b, vdata.16b, vrepchr.16b
89 cmeq vhas_nul.16b, vdata.16b, #0
90 cmeq vhas_chr.16b, vdata.16b, vrepchr.16b
98 cmeq vhas_nul.16b, vdata.16b, #0
99 cmeq vhas_chr.16b, vdata.16b, vrepchr.16b
|
| /llvm-project-15.0.7/llvm/docs/AMDGPU/ |
| H A D | AMDGPUAsmGFX7.rst | 45 … :ref:`vaddr<amdgpu_synid_gfx7_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx7_…
46 … :ref:`vaddr<amdgpu_synid_gfx7_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx7_…
70 …ds_gws_barrier :ref:`vdata<amdgpu_synid_gfx7_vdata_6802ce>` …
71 …ds_gws_init :ref:`vdata<amdgpu_synid_gfx7_vdata_6802ce>` …
72 …ds_gws_sema_br :ref:`vdata<amdgpu_synid_gfx7_vdata_6802ce>` …
235 … :ref:`vaddr<amdgpu_synid_gfx7_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx7_…
236 … :ref:`vaddr<amdgpu_synid_gfx7_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx7_…
237 … :ref:`vaddr<amdgpu_synid_gfx7_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx7_…
238 … :ref:`vaddr<amdgpu_synid_gfx7_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx7_…
239 … :ref:`vaddr<amdgpu_synid_gfx7_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx7_…
[all …]
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| H A D | AMDGPUAsmGFX90a.rst | 41 … :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx90…
42 … :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx90…
47 … :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx90…
48 … :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx90…
49 … :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx90…
50 … :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx90…
67 … :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx90…
69 …ds_gws_barrier :ref:`vdata<amdgpu_synid_gfx90a_vdata_be4895>` …
70 …ds_gws_init :ref:`vdata<amdgpu_synid_gfx90a_vdata_be4895>` …
71 …ds_gws_sema_br :ref:`vdata<amdgpu_synid_gfx90a_vdata_be4895>` …
[all …]
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| H A D | AMDGPUAsmGFX1030.rst | 259 … :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx10…
263 … :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx10…
264 … :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx10…
265 … :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx10…
266 … :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx10…
283 … :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx10…
284 … :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx10…
285 …ds_gws_barrier :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>` …
286 …ds_gws_init :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>` …
287 …ds_gws_sema_br :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>` …
[all …]
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| H A D | AMDGPUAsmGFX10.rst | 255 … :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx10…
262 … :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx10…
263 … :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx10…
264 … :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx10…
265 … :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx10…
286 … :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx10…
287 … :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx10…
288 …ds_gws_barrier :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>` …
289 …ds_gws_init :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>` …
290 …ds_gws_sema_br :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>` …
[all …]
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| H A D | AMDGPUAsmGFX9.rst | 41 … :ref:`vaddr<amdgpu_synid_gfx9_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx9_…
48 … :ref:`vaddr<amdgpu_synid_gfx9_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx9_…
49 … :ref:`vaddr<amdgpu_synid_gfx9_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx9_…
50 … :ref:`vaddr<amdgpu_synid_gfx9_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx9_…
51 … :ref:`vaddr<amdgpu_synid_gfx9_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx9_…
72 … :ref:`vaddr<amdgpu_synid_gfx9_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx9_…
73 … :ref:`vaddr<amdgpu_synid_gfx9_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx9_…
74 …ds_gws_barrier :ref:`vdata<amdgpu_synid_gfx9_vdata_6802ce>` …
75 …ds_gws_init :ref:`vdata<amdgpu_synid_gfx9_vdata_6802ce>` …
76 …ds_gws_sema_br :ref:`vdata<amdgpu_synid_gfx9_vdata_6802ce>` …
[all …]
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| H A D | AMDGPUAsmGFX940.rst | 41 … :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx94…
42 … :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx94…
47 … :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx94…
48 … :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx94…
49 … :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx94…
50 … :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx94…
67 … :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx94…
69 …ds_gws_barrier :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>` …
70 …ds_gws_init :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>` …
71 …ds_gws_sema_br :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>` …
[all …]
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| H A D | AMDGPUAsmGFX8.rst | 41 … :ref:`vaddr<amdgpu_synid_gfx8_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx8_…
48 … :ref:`vaddr<amdgpu_synid_gfx8_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx8_…
74 …ds_gws_barrier :ref:`vdata<amdgpu_synid_gfx8_vdata_6802ce>` …
75 …ds_gws_init :ref:`vdata<amdgpu_synid_gfx8_vdata_6802ce>` …
76 …ds_gws_sema_br :ref:`vdata<amdgpu_synid_gfx8_vdata_6802ce>` …
236 … :ref:`vaddr<amdgpu_synid_gfx8_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx8_…
237 … :ref:`vaddr<amdgpu_synid_gfx8_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx8_…
238 … :ref:`vaddr<amdgpu_synid_gfx8_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx8_…
239 … :ref:`vaddr<amdgpu_synid_gfx8_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx8_…
240 … :ref:`vaddr<amdgpu_synid_gfx8_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx8_…
[all …]
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| H A D | gfx1030_vdata_56f215.rst | 10 vdata title
|
| H A D | gfx1030_vdata_e016a1.rst | 10 vdata title
|
| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | MIMGInstructions.td | 34 // vdata/vaddr size.
553 let InOperandList = !con((ins DataRC:$vdata),
579 let InOperandList = !con((ins DataRC:$vdata),
674 let Constraints = "$vdst = $vdata";
686 let Constraints = "$vdst = $vdata";
722 let Constraints = "$vdst = $vdata";
736 let Constraints = "$vdst = $vdata";
739 let InOperandList = !con((ins DataRC:$vdata),
752 let Constraints = "$vdst = $vdata";
766 let Constraints = "$vdst = $vdata";
[all …]
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| H A D | BUFInstructions.td | 125 bits<10> vdata;
135 bits<1> acc = !if(ps.has_vdata, vdata{9}, 0);
364 bits<10> vdata;
660 (ins vdata_op:$vdata,
662 (ins vdata_op:$vdata, vaddrClass:$vaddr,
736 (outs vdata_op:$vdata),
746 let Constraints = "$vdata = $vdata_in";
780 [(set vdataType:$vdata,
787 [(set vdataType:$vdata,
1356 getVregSrcForVT<vt>.ret:$vdata,
[all …]
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| /llvm-project-15.0.7/mlir/include/mlir/Dialect/LLVMIR/ |
| H A D | ROCDLOps.td | 185 Arguments<(ins LLVM_Type:$vdata,
194 llvm::Intrinsic::amdgcn_buffer_store, {$vdata, $rsrc, $vindex,
220 Arguments<(ins LLVM_Type:$vdata,
228 llvm::Intrinsic::amdgcn_raw_buffer_store, {$vdata, $rsrc,
239 Arguments<(ins LLVM_Type:$vdata,
247 llvm::Intrinsic::amdgcn_raw_buffer_atomic_fadd, {$vdata, $rsrc,
|
| /llvm-project-15.0.7/llvm/docs/ |
| H A D | AMDGPUInstructionNotation.rst | 80 vdata // operand only accepts vector registers
112 vdata:dst // vdata operand may be used as both source and destination
|