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Searched refs:vc1 (Results 1 – 8 of 8) sorted by relevance

/llvm-project-15.0.7/compiler-rt/lib/tsan/tests/unit/
H A Dtsan_vector_clock_test.cpp35 VectorClock *vc1 = New<VectorClock>(); in TEST() local
39 vc1->Acquire(vc2); in TEST()
42 vc1->Release(&vc2); in TEST()
44 vc1->Acquire(vc2); in TEST()
52 vc1->Acquire(vc2); in TEST()
54 ASSERT_EQ(vc1->Get(static_cast<Sid>(i)), in TEST()
68 vc1->Reset(); in TEST()
74 vc1->ReleaseAcquire(&vc2); in TEST()
82 vc1->Reset(); in TEST()
88 vc1->ReleaseStoreAcquire(&vc2); in TEST()
[all …]
/llvm-project-15.0.7/clang/test/CodeGen/PowerPC/
H A Dbuiltins-ppc-build-pair-mma.c21 void test1(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc1, vector unsigned char v… in test1() argument
26 __builtin_mma_build_acc(&res, vc1, vc2, vc3, vc4); in test1()
44 void test2(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc1, in test2() argument
49 __builtin_vsx_build_pair(&res, vc1, vc2); in test2()
/llvm-project-15.0.7/clang/test/CodeGen/
H A DNontemporal.cpp15 char __attribute__((vector_size(8))) vc1, vc2; variable
33 __builtin_nontemporal_store(vc1, &vc2); // CHECK: store <8 x i8>{{.*}}align 8, !nontemporal in test_all_sizes()
47 vc2 = __builtin_nontemporal_load(&vc1); // CHECK: load <8 x i8>{{.*}}align 8, !nontemporal in test_all_sizes()
/llvm-project-15.0.7/llvm/test/CodeGen/Thumb2/
H A Dmve-pred-build-var.ll49 %vc1 = insertelement <4 x i1> undef, i1 %c, i64 0
50 %vc4 = shufflevector <4 x i1> %vc1, <4 x i1> undef, <4 x i32> zeroinitializer
100 %vc1 = insertelement <8 x i1> undef, i1 %c, i64 0
101 %vc4 = shufflevector <8 x i1> %vc1, <8 x i1> undef, <8 x i32> zeroinitializer
151 %vc1 = insertelement <16 x i1> undef, i1 %c, i64 0
152 %vc4 = shufflevector <16 x i1> %vc1, <16 x i1> undef, <16 x i32> zeroinitializer
202 %vc1 = insertelement <2 x i1> undef, i1 %c, i64 0
203 %vc4 = shufflevector <2 x i1> %vc1, <2 x i1> undef, <2 x i32> zeroinitializer
/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A Daix-emit-tracebacktable-vectorinfo.ll10 …tor float f(vector int vi1, int i1, int i2, float f1, vector float vf,double d1, vector char vc1) {
19 …vi1, i32 signext %i1, i32 signext %i2, float %f1, <4 x float> %vf, double %d1, <16 x i8> %vc1) #0 {
28 %vc1.addr = alloca <16 x i8>, align 16
35 store <16 x i8> %vc1, <16 x i8>* %vc1.addr, align 16
H A Dmma-acc-spill.ll12 define void @intrinsics1(<16 x i8> %vc1, <16 x i8> %vc2, <16 x i8> %vc3, <16 x i8> %vc4, ptr %ptr) {
115 …%1 = tail call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> %vc1, <16 x i8> %vc2, <16 x i8> %vc…
116 %2 = tail call <512 x i1> @llvm.ppc.mma.xvf16ger2pp(<512 x i1> %1, <16 x i8> %vc1, <16 x i8> %vc3)
118 %3 = tail call <512 x i1> @llvm.ppc.mma.xvf16ger2pp(<512 x i1> %2, <16 x i8> %vc1, <16 x i8> %vc3)
H A Dmma-outer-product.ll11 define void @intrinsics1(<16 x i8> %vc1, <16 x i8> %vc2, <16 x i8> %vc3, <16 x i8> %vc4, ptr %ptr) {
59 …%1 = tail call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> %vc1, <16 x i8> %vc3, <16 x i8> %vc…
60 %2 = tail call <512 x i1> @llvm.ppc.mma.xvi4ger8pp(<512 x i1> %1, <16 x i8> %vc1, <16 x i8> %vc2)
61 %3 = tail call <512 x i1> @llvm.ppc.mma.xvf16ger2pp(<512 x i1> %2, <16 x i8> %vc1, <16 x i8> %vc3)
63 %5 = tail call <256 x i1> @llvm.ppc.vsx.assemble.pair(<16 x i8> %vc4, <16 x i8> %vc1)
64 …%6 = tail call <512 x i1> @llvm.ppc.mma.pmxvf64gernp(<512 x i1> %4, <256 x i1> %5, <16 x i8> %vc1,…
118 %vc1 = load <16 x i8>, ptr %ptr1, align 16
123 %2 = tail call <512 x i1> @llvm.ppc.mma.xvi8ger4pp(<512 x i1> %1, <16 x i8> %vc1, <16 x i8> %vc2)
124 %3 = tail call <512 x i1> @llvm.ppc.mma.xvf16ger2pn(<512 x i1> %2, <16 x i8> %vc1, <16 x i8> %vc3)
126 %5 = tail call <256 x i1> @llvm.ppc.vsx.assemble.pair(<16 x i8> %vc4, <16 x i8> %vc1)
[all …]
/llvm-project-15.0.7/mlir/test/Dialect/SPIRV/Transforms/
H A Dcanonicalize.mlir230 %vc1 = spv.Constant dense<[42, -55, 127]> : vector<3xi32>
234 %0 = spv.IAdd %vc1, %vc2 : vector<3xi32>
294 %vc1 = spv.Constant dense<[42, -55, 127]> : vector<3xi32>
298 %0 = spv.IMul %vc1, %vc2 : vector<3xi32>
356 %vc1 = spv.Constant dense<[42, -55, 127]> : vector<3xi32>
360 %0 = spv.ISub %vc1, %vc2 : vector<3xi32>