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Searched refs:valign (Results 1 – 25 of 25) sorted by relevance

/llvm-project-15.0.7/llvm/test/CodeGen/Hexagon/autohvx/
H A Disel-expand-unaligned-loads.ll6 ; CHECK: valign(v[[V01]],v[[V00]],r[[B00]])
18 ; CHECK-DAG: valign(v[[V11]],v[[V10]],r[[B01]])
19 ; CHECK-DAG: valign(v[[V12]],v[[V11]],r[[B01]])
H A Dalign2-64b.ll12 ; CHECK: v0 = valign(v0,v0,#1)
20 ; CHECK: v0 = valign(v0,v0,#2)
28 ; CHECK: v0 = valign(v0,v0,#3)
36 ; CHECK: v0 = valign(v0,v0,#4)
44 ; CHECK: v0 = valign(v0,v0,#5)
52 ; CHECK: v0 = valign(v0,v0,#6)
60 ; CHECK: v0 = valign(v0,v0,#7)
573 ; CHECK: v0 = valign(v0,v1,#1)
581 ; CHECK: v0 = valign(v0,v1,#2)
589 ; CHECK: v0 = valign(v0,v1,#3)
[all …]
H A Dalign2-128b.ll12 ; CHECK: v0 = valign(v0,v0,#1)
20 ; CHECK: v0 = valign(v0,v0,#2)
28 ; CHECK: v0 = valign(v0,v0,#3)
36 ; CHECK: v0 = valign(v0,v0,#4)
44 ; CHECK: v0 = valign(v0,v0,#5)
52 ; CHECK: v0 = valign(v0,v0,#6)
60 ; CHECK: v0 = valign(v0,v0,#7)
1149 ; CHECK: v0 = valign(v0,v1,#1)
1157 ; CHECK: v0 = valign(v0,v1,#2)
1165 ; CHECK: v0 = valign(v0,v1,#3)
[all …]
H A Dalign-64b.ll4 ; CHECK-NOT: valign
11 ; CHECK: valign(v1,v0,#1)
18 ; CHECK: valign(v1,v0,#2)
25 ; CHECK: valign(v1,v0,#3)
32 ; CHECK: valign(v1,v0,#4)
39 ; CHECK: valign(v1,v0,#5)
46 ; CHECK: valign(v1,v0,#6)
53 ; CHECK: valign(v1,v0,#7)
61 ; CHECK: valign(v1,v0,[[R0008]])
69 ; CHECK: valign(v1,v0,[[R0009]])
[all …]
H A Dalign-128b.ll4 ; CHECK-NOT: valign
11 ; CHECK: valign(v1,v0,#1)
18 ; CHECK: valign(v1,v0,#2)
25 ; CHECK: valign(v1,v0,#3)
32 ; CHECK: valign(v1,v0,#4)
39 ; CHECK: valign(v1,v0,#5)
46 ; CHECK: valign(v1,v0,#6)
53 ; CHECK: valign(v1,v0,#7)
61 ; CHECK: valign(v1,v0,[[R0008]])
69 ; CHECK: valign(v1,v0,[[R0009]])
[all …]
H A Disel-shuffle-pack.ll5 ; CHECK: valign
H A Dvector-align-basic.ll30 ; CHECK-NEXT: v1 = valign(v1,v0,r7)
H A Dshuffle-half-64b.ll97 ; CHECK-NEXT: v0 = valign(v1,v0,r7)
184 ; CHECK-NEXT: v0 = valign(v0,v1,r7)
H A Dshuffle-half-128b.ll97 ; CHECK-NEXT: v0 = valign(v1,v0,r7)
184 ; CHECK-NEXT: v0 = valign(v0,v1,r7)
/llvm-project-15.0.7/llvm/test/CodeGen/Hexagon/
H A Dnv_store_vec.ll5 ; CHECK: v{{[0-9]+}} = valign(v{{[0-9]+}},v{{[0-9]+}},r{{[0-9]+}})
H A Dbitconvert-vector.ll5 ; CHECK: valign
H A Dmulti-cycle.ll6 ; CHECK: v{{[0-9]+}} = valign(v{{[0-9]+}},v{{[0-9]+}},#2)
9 ; CHECK: v{{[0-9]+}} = valign(v{{[0-9]+}},v{{[0-9]+}},#2)
H A Dhvx-bitcast-v64i1.ll5 ; CHECK: valign
H A Dstore-vector-pred.ll5 ; CHECK: valign
H A Dswp-intreglow8.ll6 ; In this case, the register class of a valign scalar operand changed
H A Dintrinsics-v60-misc.ll64 ; CHECK: v{{[0-9]+}} = valign(v{{[0-9]+}},v{{[0-9]+}},r{{[0-9]+}})
163 ; CHECK: v{{[0-9]+}} = valign(v{{[0-9]+}},v{{[0-9]+}},#3)
H A Dv60Intrins.ll110 ; CHECK: v{{[0-9]*}} = valign(v{{[0-9]*}},v{{[0-9]*}},#1)
111 ; CHECK: v{{[0-9]*}} = valign(v{{[0-9]*}},v{{[0-9]*}},r{{[0-9]*}})
/llvm-project-15.0.7/llvm/docs/_static/
H A DLoopOptWG_invite.ics35 …ht: 50px;" align="left" class="main">\n <tr>\n <td align="center" valign="top" >&nbsp; …
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonPatternsHVX.td629 def: Pat<(VecI8 (valign HVI8:$Vt, HVI8:$Vs, I32:$Rt)),
631 def: Pat<(VecI16 (valign HVI16:$Vt, HVI16:$Vs, I32:$Rt)),
633 def: Pat<(VecI32 (valign HVI32:$Vt, HVI32:$Vs, I32:$Rt)),
H A DHexagonISelDAGToDAGHVX.cpp1129 auto valign = [this](OpRef Lo, OpRef Hi, unsigned Amt, MVT Ty, in packs() local
1296 OpRef RetVal = valign(Va, Vb, ShiftR, Ty, Results); in packs()
H A DHexagonPatterns.td105 def valign: PatFrag<(ops node:$Vt, node:$Vs, node:$Ru),
H A DHexagonDepInstrInfo.td31027 "$Vd32 = valign($Vu32,$Vv32,$Rt8)",
31040 "$Vd32 = valign($Vu32,$Vv32,#$Ii)",
/llvm-project-15.0.7/llvm/test/MC/Hexagon/extensions/
H A Dv67_hvx.s969 v0=valign(v0,v0,r0)
970 # CHECK-NEXT: 1b00c000 { v0 = valign(v0,v0,r0) }
974 v0=valign(v0,v0,#0)
975 # CHECK-NEXT: 1e20e000 { v0 = valign(v0,v0,#0) }
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Davx512vl-intrinsics-upgrade.ll8825 declare <4 x i32> @llvm.x86.avx512.mask.valign.d.128(<4 x i32>, <4 x i32>, i32, <4 x i32>, i8)
8833 …%res = call <4 x i32> @llvm.x86.avx512.mask.valign.d.128(<4 x i32> %x0, <4 x i32> %x1, i32 2, <4 x…
8854 …%res = call <4 x i32> @llvm.x86.avx512.mask.valign.d.128(<4 x i32> %x0, <4 x i32> %x1, i32 2, <4 x…
8877 declare <8 x i32> @llvm.x86.avx512.mask.valign.d.256(<8 x i32>, <8 x i32>, i32, <8 x i32>, i8)
8885 …%res = call <8 x i32> @llvm.x86.avx512.mask.valign.d.256(<8 x i32> %x0, <8 x i32> %x1, i32 6, <8 x…
8906 …%res = call <8 x i32> @llvm.x86.avx512.mask.valign.d.256(<8 x i32> %x0, <8 x i32> %x1, i32 6, <8 x…
8910 declare <2 x i64> @llvm.x86.avx512.mask.valign.q.128(<2 x i64>, <2 x i64>, i32, <2 x i64>, i8)
8918 …%res = call <2 x i64> @llvm.x86.avx512.mask.valign.q.128(<2 x i64> %x0, <2 x i64> %x1, i32 1, <2 x…
8939 …%res = call <2 x i64> @llvm.x86.avx512.mask.valign.q.128(<2 x i64> %x0, <2 x i64> %x1, i32 1, <2 x…
8943 declare <4 x i64> @llvm.x86.avx512.mask.valign.q.256(<4 x i64>, <4 x i64>, i32, <4 x i64>, i8)
[all …]
H A Davx512-intrinsics-upgrade.ll5129 …%res = call <8 x i64> @llvm.x86.avx512.mask.valign.q.512(<8 x i64> %a, <8 x i64> %b, i32 2, <8 x i…
5150 …%res = call <8 x i64> @llvm.x86.avx512.mask.valign.q.512(<8 x i64> %a, <8 x i64> %b, i32 2, <8 x i…
5154 declare <8 x i64> @llvm.x86.avx512.mask.valign.q.512(<8 x i64>, <8 x i64>, i32, <8 x i64>, i8)
5170 …%res = call <16 x i32> @llvm.x86.avx512.mask.valign.d.512(<16 x i32> %a, <16 x i32> %b, i32 5, <16…
5174 declare <16 x i32> @llvm.x86.avx512.mask.valign.d.512(<16 x i32>, <16 x i32>, i32, <16 x i32>, i16)