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Searched refs:val7 (Results 1 – 25 of 127) sorted by relevance

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/llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/
H A Dspill-01.ll92 %val7 = load i32, i32 *%ptr7
104 store i32 %val7, i32 *%ptr7
134 %val7 = load i64, i64 *%ptr7
146 store i64 %val7, i64 *%ptr7
180 %val7 = load float, float *%ptr7
193 store float %val7, float *%ptr7
237 store double %val7, double *%ptr7
334 %val7 = load i32, i32 *@g7
347 store i32 %val7, i32 *@g7
366 %val7 = load i64, i64 *@h7
[all …]
H A Dcond-move-10.ll33 %val7 = load i64, i64 *%ptr7
46 %add7 = add i64 %add6, %val7
79 %val7 = load i32, i32 *%ptr7
92 %add7 = add i32 %add6, %val7
H A Dint-add-11.ll144 %val7 = load volatile i32, i32 *%ptr
165 %add7 = add i32 %val7, 127
184 %new7 = phi i32 [ %val7, %entry ], [ %add7, %add ]
227 %val7 = load volatile i32, i32 *%ptr
248 %add7 = add i32 %val7, -128
267 %new7 = phi i32 [ %val7, %entry ], [ %add7, %add ]
H A Dint-add-12.ll143 %val7 = load volatile i64, i64 *%ptr
164 %add7 = add i64 %val7, 127
183 %new7 = phi i64 [ %val7, %entry ], [ %add7, %add ]
226 %val7 = load volatile i64, i64 *%ptr
247 %add7 = add i64 %val7, -128
266 %new7 = phi i64 [ %val7, %entry ], [ %add7, %add ]
H A Dfp-conv-03.ll104 %val7 = load volatile float, float *%ptr2
122 %ext7 = fpext float %val7 to fp128
140 store volatile float %val7, float *%ptr2
H A Dfp-conv-04.ll104 %val7 = load volatile double, double *%ptr2
122 %ext7 = fpext double %val7 to fp128
140 store volatile double %val7, double *%ptr2
H A Dfp-sqrt-02.ll91 %val7 = load volatile double, double *%ptr
109 %sqrt7 = call double @llvm.sqrt.f64(double %val7)
127 store volatile double %val7, double *%ptr
H A Dfp-sqrt-01.ll91 %val7 = load volatile float, float *%ptr
109 %sqrt7 = call float @llvm.sqrt.f32(float %val7)
127 store volatile float %val7, float *%ptr
H A Dint-conv-11.ll18 %val7 = load volatile i32, i32 *%ptr
51 %trunc7 = trunc i32 %val7 to i8
117 store volatile i32 %val7, i32 *%ptr
191 %val7 = load volatile i32, i32 *%ptr
224 %trunc7 = trunc i32 %val7 to i16
290 store volatile i32 %val7, i32 *%ptr
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dfloatdp_2source.ll26 %val7 = fsub float -0.0, %val6
29 store volatile float %val7, float* @varfloat
54 %val7 = fsub double -0.0, %val6
57 store volatile double %val7, double* @vardouble
H A Dregress-w29-reserved-with-fp.ll16 %val7 = load volatile i32, i32* @var
31 store volatile i32 %val7, i32* @var
H A Daddsub-shifted.ll57 %val7 = sub i64 %lhs64, %shift7
58 store volatile i64 %val7, i64* @var64
118 %val7 = sub i64 %lhs64, %shift7
119 store volatile i64 %val7, i64* @var64
177 %val7 = sub i64 %lhs64, %shift7
178 store volatile i64 %val7, i64* @var64
H A Dcallee-save.ll21 %val7 = load volatile float, float* @var
54 store volatile float %val7, float* @var
/llvm-project-15.0.7/libc/test/src/__support/
H A Duint128_test.cpp63 LL_UInt128 val7(2); in TEST() local
66 EXPECT_EQ((val7 * val8), result4); in TEST()
67 EXPECT_EQ((val7 * val8), (val8 * val7)); in TEST()
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dblock_set.ll52 %val7 = call i1 @foo()
53 ret i1 %val7
H A Dmerge-consecutive-loads-512.ll91 %val7 = load double, ptr %ptr7
94 %res7 = insertelement <8 x double> %res1, double %val7, i32 7
142 %val7 = load double, ptr %ptr7
147 %res7 = insertelement <8 x double> %res5, double %val7, i32 7
221 %val7 = load i64, ptr %ptr7
226 %res7 = insertelement <8 x i64> %res5, i64 %val7, i32 7
541 %val7 = load i8, ptr %ptr7
545 %res7 = insertelement <64 x i8> %res3, i8 %val7, i8 7
608 %val7 = load double, ptr %ptr7
611 %res7 = insertelement <8 x double> %res1, double %val7, i32 7
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dgpr-paired-spill-thumbinst.ll15 %val7 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr)
28 store volatile i64 %val7, i64* %addr
H A Dgpr-paired-spill.ll12 %val7 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr)
42 store volatile i64 %val7, i64* %addr
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/
H A Dnacl-reserved-regs.ll14 %val7 = load volatile i32, i32* @var
30 store volatile i32 %val7, i32* @var
/llvm-project-15.0.7/llvm/test/Transforms/SimpleLoopUnswitch/
H A D2011-09-26-EHCrash.ll48 %lpad.val7 = insertvalue { i8*, i32 } %lpad.val, i32 %3, 1
49 resume { i8*, i32 } %lpad.val7
/llvm-project-15.0.7/polly/test/ScopDetect/
H A Dprofitability-large-basic-blocks.ll38 %val7 = fadd float %val6, 1.0
39 %val8 = fadd float %val7, 1.0
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dsgpr-spill-incorrect-fi-bookkeeping-bug.ll20 %val7 = call <16 x i32> asm sideeffect "; def $0", "=s" () #0
40 call void asm sideeffect "; use $0", "s"(<16 x i32> %val7) #0
H A Dattr-amdgpu-num-vgpr.ll16 %val7 = load volatile float, float addrspace(1)* @var
48 store volatile float %val7, float addrspace(1)* @var
/llvm-project-15.0.7/llvm/test/CodeGen/Thumb/
H A Dragreedy-implicit-def.ll30 %val7 = load i32, i32* %gep7, align 4
41 %phi7a = phi i32 [ %val7, %if ], [ undef, %entry ]
/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/
H A Dcompress.ll95 %val7 = load volatile i32, i32* %b
96 %tst4 = icmp uge i32 %val6, %val7
97 %val8 = select i1 %tst4, i32 %val6, i32 %val7

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