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Searched refs:val6 (Results 1 – 25 of 131) sorted by relevance

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/llvm-project-15.0.7/llvm/test/Analysis/CostModel/SystemZ/
H A Dscalar-cmp-cmp-log-sel.ll8 i8 %val5, i8 %val6) {
12 %sel = select i1 %and, i8 %val5, i8 %val6
23 i16 %val5, i16 %val6) {
38 i32 %val5, i32 %val6) {
53 i64 %val5, i64 %val6) {
98 i8 %val5, i8 %val6) {
113 i16 %val5, i16 %val6) {
128 i32 %val5, i32 %val6) {
188 i8 %val5, i8 %val6) {
278 i8 %val5, i8 %val6) {
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/
H A Dvec-cmp-cmp-logic-select.ll19 %sel = select <2 x i1> %and, <2 x i8> %val5, <2 x i8> %val6
35 %sel = select <2 x i1> %and, <2 x i16> %val5, <2 x i16> %val6
52 %sel = select <16 x i1> %and, <16 x i8> %val5, <16 x i8> %val6
98 %sel = select <32 x i1> %and, <32 x i8> %val5, <32 x i8> %val6
114 %sel = select <2 x i1> %and, <2 x i8> %val5, <2 x i8> %val6
130 %sel = select <2 x i1> %and, <2 x i16> %val5, <2 x i16> %val6
147 %sel = select <2 x i1> %and, <2 x i32> %val5, <2 x i32> %val6
163 %sel = select <8 x i1> %and, <8 x i8> %val5, <8 x i8> %val6
178 %sel = select <8 x i1> %and, <8 x i16> %val5, <8 x i16> %val6
197 %sel = select <8 x i1> %and, <8 x i32> %val5, <8 x i32> %val6
[all …]
H A Dspill-01.ll53 %val6 = load i32, i32 *%ptr6
63 store i32 %val6, i32 *%ptr6
91 %val6 = load i32, i32 *%ptr6
103 store i32 %val6, i32 *%ptr6
133 %val6 = load i64, i64 *%ptr6
145 store i64 %val6, i64 *%ptr6
192 store float %val6, float *%ptr6
333 %val6 = load i32, i32 *@g6
346 store i32 %val6, i32 *@g6
365 %val6 = load i64, i64 *@h6
[all …]
H A Dcond-move-10.ll32 %val6 = load i64, i64 *%ptr6
45 %add6 = add i64 %add5, %val6
78 %val6 = load i32, i32 *%ptr6
91 %add6 = add i32 %add5, %val6
H A Dint-add-11.ll143 %val6 = load volatile i32, i32 *%ptr
164 %add6 = add i32 %val6, 127
183 %new6 = phi i32 [ %val6, %entry ], [ %add6, %add ]
226 %val6 = load volatile i32, i32 *%ptr
247 %add6 = add i32 %val6, -128
266 %new6 = phi i32 [ %val6, %entry ], [ %add6, %add ]
H A Dint-add-12.ll142 %val6 = load volatile i64, i64 *%ptr
163 %add6 = add i64 %val6, 127
182 %new6 = phi i64 [ %val6, %entry ], [ %add6, %add ]
225 %val6 = load volatile i64, i64 *%ptr
246 %add6 = add i64 %val6, -128
265 %new6 = phi i64 [ %val6, %entry ], [ %add6, %add ]
H A Dfp-conv-03.ll103 %val6 = load volatile float, float *%ptr2
121 %ext6 = fpext float %val6 to fp128
139 store volatile float %val6, float *%ptr2
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dfloatdp_2source.ll25 %val6 = fmul float %val1, %val2
26 %val7 = fsub float -0.0, %val6
53 %val6 = fmul double %val1, %val2
54 %val7 = fsub double -0.0, %val6
H A Daddsub-shifted.ll51 %val6 = add i64 %shift6, %lhs64
52 store volatile i64 %val6, i64* @var64
113 %val6 = add i64 %shift6, %lhs64
114 store volatile i64 %val6, i64* @var64
172 %val6 = add i64 %shift6, %lhs64
173 store volatile i64 %val6, i64* @var64
292 %val6 = sub i64 0, %shift6
293 %tst6 = icmp ne i64 %lhs64, %val6
H A Dregress-w29-reserved-with-fp.ll15 %val6 = load volatile i32, i32* @var
30 store volatile i32 %val6, i32* @var
H A Dcallee-save.ll20 %val6 = load volatile float, float* @var
53 store volatile float %val6, float* @var
/llvm-project-15.0.7/libc/test/src/__support/
H A Duint128_test.cpp56 LL_UInt128 val6({0x1357024675316420, 0x0123456776543210}); in TEST() local
59 EXPECT_EQ((val5 * val6), result3); in TEST()
60 EXPECT_EQ((val5 * val6), (val6 * val5)); in TEST()
/llvm-project-15.0.7/llvm/test/Transforms/LoopStrengthReduce/
H A Dwrong-hoisting-iv.ll134 %val6 = sub i32 %val4, %val5
147 %val13 = add i32 %val9, %val6
157 %val18 = add i32 %val13, %val6
162 %val21 = add i32 %val18, %val6
167 %val24 = add i32 %val21, %val6
172 %val27 = add i32 %val24, %val6
177 %val30 = add i32 %val27, %val6
182 %val33 = add i32 %val30, %val6
184 %val35 = add i32 %val33, %val6
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dblock_set.ll48 %val6 = call i1 @foo()
49 br i1 %val6, label %.header1, label %.exit, !prof !1
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dgpr-paired-spill-thumbinst.ll14 %val6 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr)
27 store volatile i64 %val6, i64* %addr
H A Dinlineasm-64bit.ll13 define void @multi_writes(i64* %p, i64 %val1, i64 %val2, i64 %val3, i64 %val4, i64 %val5, i64 %val6…
37 …"r,r,r,r,r,r,r"(i64* %p, i64 %val1, i64 %val2, i64 %val3, i64 %val4, i64 %val5, i64 %val6) nounwind
39 …r,r,r"(i64* %incdec.ptr, i64 %val1, i64 %val2, i64 %val3, i64 %val4, i64 %val5, i64 %val6) nounwind
40 …r,r,r"(i64* %incdec.ptr, i64 %val1, i64 %val2, i64 %val3, i64 %val4, i64 %val5, i64 %val6) nounwind
H A Dgpr-paired-spill.ll11 %val6 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr)
41 store volatile i64 %val6, i64* %addr
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dds_read2_offset_order.ll39 %val6 = load float, float addrspace(3)* %ptr6
40 %add6 = fadd float %add5, %val6
H A Dsgpr-spill-incorrect-fi-bookkeeping-bug.ll19 %val6 = call <8 x i32> asm sideeffect "; def $0", "=s" () #0
39 call void asm sideeffect "; use $0", "s"(<8 x i32> %val6) #0
H A Dattr-amdgpu-num-vgpr.ll15 %val6 = load volatile float, float addrspace(1)* @var
47 store volatile float %val6, float addrspace(1)* @var
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/
H A Dnacl-reserved-regs.ll13 %val6 = load volatile i32, i32* @var
29 store volatile i32 %val6, i32* @var
/llvm-project-15.0.7/clang/test/SemaCXX/
H A Dimaginary-constants.cpp15 _Complex long double val6 = 2.0il; variable
/llvm-project-15.0.7/polly/test/ScopDetect/
H A Dprofitability-large-basic-blocks.ll37 %val6 = fadd float %val5, 1.0
38 %val7 = fadd float %val6, 1.0
/llvm-project-15.0.7/llvm/test/CodeGen/Thumb/
H A Dragreedy-implicit-def.ll29 %val6 = load i32, i32* %gep6, align 4
40 %phi6a = phi i32 [ %val6, %if ], [ undef, %entry ]
/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/
H A Dcompress.ll93 %val6 = select i1 %tst3, i32 %val4, i32 %val5
96 %tst4 = icmp uge i32 %val6, %val7
97 %val8 = select i1 %tst4, i32 %val6, i32 %val7

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