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Searched refs:val5 (Results 1 – 25 of 147) sorted by relevance

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/llvm-project-15.0.7/llvm/test/Analysis/CostModel/SystemZ/
H A Dscalar-cmp-cmp-log-sel.ll8 i8 %val5, i8 %val6) {
12 %sel = select i1 %and, i8 %val5, i8 %val6
23 i16 %val5, i16 %val6) {
38 i32 %val5, i32 %val6) {
53 i64 %val5, i64 %val6) {
98 i8 %val5, i8 %val6) {
113 i16 %val5, i16 %val6) {
128 i32 %val5, i32 %val6) {
188 i8 %val5, i8 %val6) {
278 i8 %val5, i8 %val6) {
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/
H A Dvec-cmp-cmp-logic-select.ll19 %sel = select <2 x i1> %and, <2 x i8> %val5, <2 x i8> %val6
35 %sel = select <2 x i1> %and, <2 x i16> %val5, <2 x i16> %val6
52 %sel = select <16 x i1> %and, <16 x i8> %val5, <16 x i8> %val6
98 %sel = select <32 x i1> %and, <32 x i8> %val5, <32 x i8> %val6
114 %sel = select <2 x i1> %and, <2 x i8> %val5, <2 x i8> %val6
130 %sel = select <2 x i1> %and, <2 x i16> %val5, <2 x i16> %val6
147 %sel = select <2 x i1> %and, <2 x i32> %val5, <2 x i32> %val6
163 %sel = select <8 x i1> %and, <8 x i8> %val5, <8 x i8> %val6
178 %sel = select <8 x i1> %and, <8 x i16> %val5, <8 x i16> %val6
197 %sel = select <8 x i1> %and, <8 x i32> %val5, <8 x i32> %val6
[all …]
H A Dspill-01.ll52 %val5 = load i32, i32 *%ptr5
62 store i32 %val5, i32 *%ptr5
90 %val5 = load i32, i32 *%ptr5
102 store i32 %val5, i32 *%ptr5
132 %val5 = load i64, i64 *%ptr5
144 store i64 %val5, i64 *%ptr5
191 store float %val5, float *%ptr5
332 %val5 = load i32, i32 *@g5
345 store i32 %val5, i32 *@g5
364 %val5 = load i64, i64 *@h5
[all …]
H A Dcond-move-10.ll31 %val5 = load i64, i64 *%ptr5
44 %add5 = add i64 %add4, %val5
77 %val5 = load i32, i32 *%ptr5
90 %add5 = add i32 %add4, %val5
H A Dint-add-11.ll142 %val5 = load volatile i32, i32 *%ptr
163 %add5 = add i32 %val5, 127
182 %new5 = phi i32 [ %val5, %entry ], [ %add5, %add ]
225 %val5 = load volatile i32, i32 *%ptr
246 %add5 = add i32 %val5, -128
265 %new5 = phi i32 [ %val5, %entry ], [ %add5, %add ]
H A Dint-add-12.ll141 %val5 = load volatile i64, i64 *%ptr
162 %add5 = add i64 %val5, 127
181 %new5 = phi i64 [ %val5, %entry ], [ %add5, %add ]
224 %val5 = load volatile i64, i64 *%ptr
245 %add5 = add i64 %val5, -128
264 %new5 = phi i64 [ %val5, %entry ], [ %add5, %add ]
/llvm-project-15.0.7/polly/test/ForwardOpTree/
H A Dforward_reusue.ll19 %val5 = fadd double %val4, %val4
23 store double %val5, double* %A
52 ; CHECK-NEXT: %val5 = fadd double %val4, %val4
62 ; CHECK-NEXT: %val5 = fadd double %val4, %val4
63 ; CHECK-NEXT: store double %val5, double* %A, align 8
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dfloatdp_2source.ll19 %val5 = fsub float %val4, %val2
22 store volatile float %val5, float* @varfloat
47 %val5 = fsub double %val4, %val2
50 store volatile double %val5, double* @vardouble
H A Darm64-extract.ll7 %val5 = or i64 %left, %right
9 ret i64 %val5
16 %val5 = or i32 %left, %right
18 ret i32 %val5
H A Dextract.ll7 %val5 = or i64 %left, %right
9 ret i64 %val5
16 %val5 = or i32 %left, %right
18 ret i32 %val5
H A Dloop-micro-op-buffer-size-t99.ll22 ; CHECK: %val5 = add nuw nsw i32 %counter, 10
65 %val5 = add i32 %counter, 10
67 store i32 %val5, i32* %xptr5
104 %val5.2 = add i32 %counter.2, 10
106 store i32 %val5.2, i32* %xptr5.2
108 store i32 %val5.2, i32* %xptr6.2
H A Daddsub-shifted.ll45 %val5 = add i64 %lhs64, %shift5
46 store volatile i64 %val5, i64* @var64
108 %val5 = add i64 %lhs64, %shift5
109 store volatile i64 %val5, i64* @var64
167 %val5 = add i64 %lhs64, %shift5
168 store volatile i64 %val5, i64* @var64
285 %val5 = sub i64 0, %shift5
286 %tst5 = icmp ne i64 %lhs64, %val5
H A Dregress-w29-reserved-with-fp.ll14 %val5 = load volatile i32, i32* @var
29 store volatile i32 %val5, i32* @var
/llvm-project-15.0.7/clang-tools-extra/test/clang-tidy/checkers/bugprone/
H A Dargument-comment-literals.cpp99 double val5 = 10.0; in test() local
100 a.foo(val5); in test()
101 a.foo(-val5); in test()
H A Dargument-comment-ignore-single-argument.cpp78 double val5 = 10.0; in test() local
79 a.foo(val5); in test()
/llvm-project-15.0.7/llvm/test/Transforms/LoopUnroll/X86/
H A Dstore_cost.ll47 %val5 = add i32 %counter, 10
49 store i32 %val5, i32* %xptr5
86 %val5.2 = add i32 %counter.2, 10
88 store i32 %val5.2, i32* %xptr5.2
90 store i32 %val5.2, i32* %xptr6.2
/llvm-project-15.0.7/libc/test/src/__support/
H A Duint128_test.cpp55 LL_UInt128 val5({2, 0}); in TEST() local
59 EXPECT_EQ((val5 * val6), result3); in TEST()
60 EXPECT_EQ((val5 * val6), (val6 * val5)); in TEST()
/llvm-project-15.0.7/llvm/test/Transforms/CodeGenPrepare/X86/
H A Dsink-addrmode-two-phi.ll13 %val2 = phi i64 * [ null, %entry ], [ %val5, %exit ]
24 %val5 = phi i64 * [ undef, %slowpath ], [ %val2, %start ]
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dbb_rotate.ll31 %val5 = call i1 @foo()
32 br i1 %val5, label %.header, label %.backedge
H A Dblock_set.ll36 %val5 = call i1 @foo()
37 br i1 %val5, label %.header2, label %.latch1, !prof !1
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dgpr-paired-spill-thumbinst.ll13 %val5 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr)
26 store volatile i64 %val5, i64* %addr
H A Dinlineasm-64bit.ll13 define void @multi_writes(i64* %p, i64 %val1, i64 %val2, i64 %val3, i64 %val4, i64 %val5, i64 %val6…
37 …"r,r,r,r,r,r,r"(i64* %p, i64 %val1, i64 %val2, i64 %val3, i64 %val4, i64 %val5, i64 %val6) nounwind
39 …r,r,r"(i64* %incdec.ptr, i64 %val1, i64 %val2, i64 %val3, i64 %val4, i64 %val5, i64 %val6) nounwind
40 …r,r,r"(i64* %incdec.ptr, i64 %val1, i64 %val2, i64 %val3, i64 %val4, i64 %val5, i64 %val6) nounwind
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dds_read2_offset_order.ll35 %val5 = load float, float addrspace(3)* %ptr5
36 %add5 = fadd float %add4, %val5
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/
H A Dnacl-reserved-regs.ll12 %val5 = load volatile i32, i32* @var
28 store volatile i32 %val5, i32* @var
/llvm-project-15.0.7/clang/test/SemaCXX/
H A Dimaginary-constants.cpp14 _Complex double val5 = 2.0i; variable

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