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/llvm-project-15.0.7/llvm/test/Analysis/CostModel/SystemZ/
H A Dcmp-ext-02.ll6 define i8 @fun0(i8 %val1, i8 %val2) {
7 %cmp = icmp eq i8 %val1, %val2
17 %cmp = icmp eq i8 %val1, %val2
27 %cmp = icmp eq i8 %val1, %val2
37 %cmp = icmp eq i8 %val1, %val2
47 %cmp = icmp eq i16 %val1, %val2
57 %cmp = icmp eq i16 %val1, %val2
67 %cmp = icmp eq i16 %val1, %val2
77 %cmp = icmp eq i16 %val1, %val2
87 %cmp = icmp eq i32 %val1, %val2
[all …]
H A Dcmp-ext-01.ll4 define i8 @fun0(i8 %val1, i8 %val2) {
5 %cmp = icmp eq i8 %val1, %val2
14 define i16 @fun1(i8 %val1, i8 %val2) {
15 %cmp = icmp eq i8 %val1, %val2
25 %cmp = icmp eq i8 %val1, %val2
35 %cmp = icmp eq i8 %val1, %val2
45 %cmp = icmp eq i16 %val1, %val2
55 %cmp = icmp eq i16 %val1, %val2
65 %cmp = icmp eq i16 %val1, %val2
75 %cmp = icmp eq i16 %val1, %val2
[all …]
H A Dcmpsel.ll8 define i8 @fun0(i8 %val1, i8 %val2,
10 %cmp = icmp eq i8 %val1, %val2
19 define i16 @fun1(i8 %val1, i8 %val2,
21 %cmp = icmp eq i8 %val1, %val2
32 %cmp = icmp eq i8 %val1, %val2
43 %cmp = icmp eq i8 %val1, %val2
54 %cmp = icmp eq i8 %val1, %val2
65 %cmp = icmp eq i8 %val1, %val2
76 %cmp = icmp eq i16 %val1, %val2
87 %cmp = icmp eq i16 %val1, %val2
[all …]
H A Dscalar-cmp-cmp-log-sel.ll9 %cmp0 = icmp eq i8 %val1, %val2
24 %cmp0 = icmp eq i8 %val1, %val2
39 %cmp0 = icmp eq i8 %val1, %val2
54 %cmp0 = icmp eq i8 %val1, %val2
69 %cmp0 = icmp eq i8 %val1, %val2
84 %cmp0 = icmp eq i8 %val1, %val2
99 %cmp0 = icmp eq i16 %val1, %val2
114 %cmp0 = icmp eq i16 %val1, %val2
129 %cmp0 = icmp eq i16 %val1, %val2
144 %cmp0 = icmp eq i16 %val1, %val2
[all …]
/llvm-project-15.0.7/libcxx/test/libcxx/atomics/
H A Ddiagnose_invalid_memory_order.verify.cpp24 int val1 = 1; ((void)val1); in main() local
81 x.compare_exchange_weak(val1, val2, std::memory_order_seq_cst, std::memory_order_relaxed); in main()
82 x.compare_exchange_weak(val1, val2, std::memory_order_seq_cst, std::memory_order_consume); in main()
83 x.compare_exchange_weak(val1, val2, std::memory_order_seq_cst, std::memory_order_acquire); in main()
84 x.compare_exchange_weak(val1, val2, std::memory_order_seq_cst, std::memory_order_seq_cst); in main()
87 x.compare_exchange_weak(val1, val2, std::memory_order_release); in main()
107 x.compare_exchange_strong(val1, val2, std::memory_order_seq_cst, std::memory_order_relaxed); in main()
108 x.compare_exchange_strong(val1, val2, std::memory_order_seq_cst, std::memory_order_consume); in main()
109 x.compare_exchange_strong(val1, val2, std::memory_order_seq_cst, std::memory_order_acquire); in main()
110 x.compare_exchange_strong(val1, val2, std::memory_order_seq_cst, std::memory_order_seq_cst); in main()
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dvsel.ll8 store float %val1, float* @varfloat
17 store double %val1, double* @vardouble
26 store float %val1, float* @varfloat
35 store double %val1, double* @vardouble
44 store float %val1, float* @varfloat
62 store float %val1, float* @varfloat
80 store float %val1, float* @varfloat
98 store float %val1, float* @varfloat
116 store float %val1, float* @varfloat
134 store float %val1, float* @varfloat
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/
H A Dvec-min-02.ll6 define <8 x i16> @f1(<8 x i16> %val1, <8 x i16> %val2) {
10 %cmp = icmp slt <8 x i16> %val2, %val1
16 define <8 x i16> @f2(<8 x i16> %val1, <8 x i16> %val2) {
20 %cmp = icmp sle <8 x i16> %val2, %val1
26 define <8 x i16> @f3(<8 x i16> %val1, <8 x i16> %val2) {
30 %cmp = icmp sgt <8 x i16> %val2, %val1
40 %cmp = icmp sge <8 x i16> %val2, %val1
50 %cmp = icmp ult <8 x i16> %val2, %val1
60 %cmp = icmp ule <8 x i16> %val2, %val1
70 %cmp = icmp ugt <8 x i16> %val2, %val1
[all …]
H A Dvec-max-01.ll6 define <16 x i8> @f1(<16 x i8> %val1, <16 x i8> %val2) {
10 %cmp = icmp slt <16 x i8> %val1, %val2
16 define <16 x i8> @f2(<16 x i8> %val1, <16 x i8> %val2) {
20 %cmp = icmp sle <16 x i8> %val1, %val2
26 define <16 x i8> @f3(<16 x i8> %val1, <16 x i8> %val2) {
30 %cmp = icmp sgt <16 x i8> %val1, %val2
40 %cmp = icmp sge <16 x i8> %val1, %val2
50 %cmp = icmp ult <16 x i8> %val1, %val2
60 %cmp = icmp ule <16 x i8> %val1, %val2
70 %cmp = icmp ugt <16 x i8> %val1, %val2
[all …]
H A Dvec-max-02.ll6 define <8 x i16> @f1(<8 x i16> %val1, <8 x i16> %val2) {
10 %cmp = icmp slt <8 x i16> %val1, %val2
16 define <8 x i16> @f2(<8 x i16> %val1, <8 x i16> %val2) {
20 %cmp = icmp sle <8 x i16> %val1, %val2
26 define <8 x i16> @f3(<8 x i16> %val1, <8 x i16> %val2) {
30 %cmp = icmp sgt <8 x i16> %val1, %val2
40 %cmp = icmp sge <8 x i16> %val1, %val2
50 %cmp = icmp ult <8 x i16> %val1, %val2
60 %cmp = icmp ule <8 x i16> %val1, %val2
70 %cmp = icmp ugt <8 x i16> %val1, %val2
[all …]
H A Dvec-min-03.ll6 define <4 x i32> @f1(<4 x i32> %val1, <4 x i32> %val2) {
10 %cmp = icmp slt <4 x i32> %val2, %val1
16 define <4 x i32> @f2(<4 x i32> %val1, <4 x i32> %val2) {
20 %cmp = icmp sle <4 x i32> %val2, %val1
26 define <4 x i32> @f3(<4 x i32> %val1, <4 x i32> %val2) {
30 %cmp = icmp sgt <4 x i32> %val2, %val1
40 %cmp = icmp sge <4 x i32> %val2, %val1
50 %cmp = icmp ult <4 x i32> %val2, %val1
60 %cmp = icmp ule <4 x i32> %val2, %val1
70 %cmp = icmp ugt <4 x i32> %val2, %val1
[all …]
H A Dvec-min-04.ll6 define <2 x i64> @f1(<2 x i64> %val1, <2 x i64> %val2) {
10 %cmp = icmp slt <2 x i64> %val2, %val1
16 define <2 x i64> @f2(<2 x i64> %val1, <2 x i64> %val2) {
20 %cmp = icmp sle <2 x i64> %val2, %val1
26 define <2 x i64> @f3(<2 x i64> %val1, <2 x i64> %val2) {
30 %cmp = icmp sgt <2 x i64> %val2, %val1
40 %cmp = icmp sge <2 x i64> %val2, %val1
50 %cmp = icmp ult <2 x i64> %val2, %val1
60 %cmp = icmp ule <2 x i64> %val2, %val1
70 %cmp = icmp ugt <2 x i64> %val2, %val1
[all …]
H A Dvec-max-04.ll6 define <2 x i64> @f1(<2 x i64> %val1, <2 x i64> %val2) {
10 %cmp = icmp slt <2 x i64> %val1, %val2
16 define <2 x i64> @f2(<2 x i64> %val1, <2 x i64> %val2) {
20 %cmp = icmp sle <2 x i64> %val1, %val2
26 define <2 x i64> @f3(<2 x i64> %val1, <2 x i64> %val2) {
30 %cmp = icmp sgt <2 x i64> %val1, %val2
40 %cmp = icmp sge <2 x i64> %val1, %val2
50 %cmp = icmp ult <2 x i64> %val1, %val2
60 %cmp = icmp ule <2 x i64> %val1, %val2
70 %cmp = icmp ugt <2 x i64> %val1, %val2
[all …]
H A Dvec-max-03.ll6 define <4 x i32> @f1(<4 x i32> %val1, <4 x i32> %val2) {
10 %cmp = icmp slt <4 x i32> %val1, %val2
16 define <4 x i32> @f2(<4 x i32> %val1, <4 x i32> %val2) {
20 %cmp = icmp sle <4 x i32> %val1, %val2
26 define <4 x i32> @f3(<4 x i32> %val1, <4 x i32> %val2) {
30 %cmp = icmp sgt <4 x i32> %val1, %val2
40 %cmp = icmp sge <4 x i32> %val1, %val2
50 %cmp = icmp ult <4 x i32> %val1, %val2
60 %cmp = icmp ule <4 x i32> %val1, %val2
70 %cmp = icmp ugt <4 x i32> %val1, %val2
[all …]
H A Dvec-min-01.ll6 define <16 x i8> @f1(<16 x i8> %val1, <16 x i8> %val2) {
10 %cmp = icmp slt <16 x i8> %val2, %val1
16 define <16 x i8> @f2(<16 x i8> %val1, <16 x i8> %val2) {
20 %cmp = icmp sle <16 x i8> %val2, %val1
26 define <16 x i8> @f3(<16 x i8> %val1, <16 x i8> %val2) {
30 %cmp = icmp sgt <16 x i8> %val2, %val1
40 %cmp = icmp sge <16 x i8> %val2, %val1
50 %cmp = icmp ult <16 x i8> %val2, %val1
60 %cmp = icmp ule <16 x i8> %val2, %val1
70 %cmp = icmp ugt <16 x i8> %val2, %val1
[all …]
H A Dvec-sext.ll7 define <2 x i16> @fun1(<2 x i8> %val1) {
11 %z = sext <2 x i8> %val1 to <2 x i16>
15 define <2 x i32> @fun2(<2 x i8> %val1) {
20 %z = sext <2 x i8> %val1 to <2 x i32>
24 define <2 x i64> @fun3(<2 x i8> %val1) {
30 %z = sext <2 x i8> %val1 to <2 x i64>
34 define <2 x i32> @fun4(<2 x i16> %val1) {
38 %z = sext <2 x i16> %val1 to <2 x i32>
47 %z = sext <2 x i16> %val1 to <2 x i64>
63 %z = sext <4 x i8> %val1 to <4 x i16>
[all …]
H A Dcall-04.ll12 define void @f1(i32 %val1, i32 %val2) {
17 %cond = icmp slt i32 %val1, %val2;
210 define void @f12(i32 %val1) {
228 define void @f13(i32 %val1) {
246 define void @f14(i32 %val1) {
264 define void @f15(i32 %val1) {
282 define void @f16(i32 %val1) {
300 define void @f17(i32 %val1) {
318 define void @f18(i32 %val1) {
336 define void @f19(i64 %val1) {
[all …]
H A Dvec-cmp-01.ll10 %cmp = icmp eq <16 x i8> %val1, %val2
21 %cmp = icmp ne <16 x i8> %val1, %val2
31 %cmp = icmp sgt <16 x i8> %val1, %val2
42 %cmp = icmp sge <16 x i8> %val1, %val2
53 %cmp = icmp sle <16 x i8> %val1, %val2
63 %cmp = icmp slt <16 x i8> %val1, %val2
73 %cmp = icmp ugt <16 x i8> %val1, %val2
84 %cmp = icmp uge <16 x i8> %val1, %val2
95 %cmp = icmp ule <16 x i8> %val1, %val2
117 %cmp = icmp eq <16 x i8> %val1, %val2
[all …]
H A Dvec-cmp-02.ll10 %cmp = icmp eq <8 x i16> %val1, %val2
21 %cmp = icmp ne <8 x i16> %val1, %val2
31 %cmp = icmp sgt <8 x i16> %val1, %val2
42 %cmp = icmp sge <8 x i16> %val1, %val2
53 %cmp = icmp sle <8 x i16> %val1, %val2
63 %cmp = icmp slt <8 x i16> %val1, %val2
73 %cmp = icmp ugt <8 x i16> %val1, %val2
84 %cmp = icmp uge <8 x i16> %val1, %val2
95 %cmp = icmp ule <8 x i16> %val1, %val2
117 %cmp = icmp eq <8 x i16> %val1, %val2
[all …]
H A Dvec-cmp-03.ll10 %cmp = icmp eq <4 x i32> %val1, %val2
21 %cmp = icmp ne <4 x i32> %val1, %val2
31 %cmp = icmp sgt <4 x i32> %val1, %val2
42 %cmp = icmp sge <4 x i32> %val1, %val2
53 %cmp = icmp sle <4 x i32> %val1, %val2
63 %cmp = icmp slt <4 x i32> %val1, %val2
73 %cmp = icmp ugt <4 x i32> %val1, %val2
84 %cmp = icmp uge <4 x i32> %val1, %val2
95 %cmp = icmp ule <4 x i32> %val1, %val2
117 %cmp = icmp eq <4 x i32> %val1, %val2
[all …]
H A Dvec-cmp-04.ll10 %cmp = icmp eq <2 x i64> %val1, %val2
21 %cmp = icmp ne <2 x i64> %val1, %val2
31 %cmp = icmp sgt <2 x i64> %val1, %val2
42 %cmp = icmp sge <2 x i64> %val1, %val2
53 %cmp = icmp sle <2 x i64> %val1, %val2
63 %cmp = icmp slt <2 x i64> %val1, %val2
73 %cmp = icmp ugt <2 x i64> %val1, %val2
84 %cmp = icmp uge <2 x i64> %val1, %val2
95 %cmp = icmp ule <2 x i64> %val1, %val2
117 %cmp = icmp eq <2 x i64> %val1, %val2
[all …]
H A Dvec-sub-01.ll10 %ret = sub <16 x i8> %val1, %val2
19 %ret = sub <8 x i16> %val1, %val2
28 %ret = sub <4 x i32> %val1, %val2
37 %ret = sub <2 x i64> %val1, %val2
63 %ret = fsub <4 x float> %val1, %val2
93 %ret = sub <2 x i8> %val1, %val2
102 %ret = sub <4 x i8> %val1, %val2
111 %ret = sub <8 x i8> %val1, %val2
120 %ret = sub <2 x i16> %val1, %val2
129 %ret = sub <4 x i16> %val1, %val2
[all …]
H A Dcall-05.ll12 define void @f1(i32 %val1, i32 %val2) {
17 %cond = icmp slt i32 %val1, %val2;
212 define void @f12(i32 %val1) {
230 define void @f13(i32 %val1) {
248 define void @f14(i32 %val1) {
266 define void @f15(i32 %val1) {
284 define void @f16(i32 %val1) {
302 define void @f17(i32 %val1) {
320 define void @f18(i32 %val1) {
338 define void @f19(i64 %val1) {
[all …]
/llvm-project-15.0.7/libc/utils/IntegrationTest/
H A Dtest.h32 #define __CHECK_EQ(file, line, val1, val2, should_exit) \ argument
33 if ((val1) != (val2)) { \
35 line) ": Expected '" #val1 "' to be equal to '" #val2 "'\n"); \
40 #define __CHECK_NE(file, line, val1, val2, should_exit) \ argument
41 if ((val1) == (val2)) { \
43 line) ": Expected '" #val1 "' to not be equal to '" #val2 "'\n"); \
52 #define EXPECT_EQ(val1, val2) \ argument
53 __CHECK_EQ(__FILE__, __LINE__, (val1), (val2), false)
55 __CHECK_EQ(__FILE__, __LINE__, (val1), (val2), true)
57 __CHECK_NE(__FILE__, __LINE__, (val1), (val2), false)
[all …]
/llvm-project-15.0.7/polly/test/ForwardOpTree/
H A Dforward_load_tripleuse.ll12 ; double val1 = A[j];
13 ; double val2 = val1 + val1;
16 ; B[j] = val1;
31 %val1 = load double, double* %A_idx
32 %val2 = fadd double %val1, %val1
37 store double %val1, double* %B_idx
71 ; CHECK-NEXT: %val2 = fadd double %val1, %val1
83 ; CHECK-NEXT: %val2 = fadd double %val1, %val1
103 %val2 = fadd double %val1, %val1
142 ; CHECK-NEXT: %val2 = fadd double %val1, %val1
[all …]
/llvm-project-15.0.7/clang/test/CodeGen/X86/
H A Dlwp-builtins.c17 unsigned char test_lwpins32(unsigned val2, unsigned val1) { in test_lwpins32() argument
20 return __lwpins32(val2, val1, 0x01234); in test_lwpins32()
23 unsigned char test_lwpins64(unsigned long long val2, unsigned val1) { in test_lwpins64() argument
26 return __lwpins64(val2, val1, 0x56789); in test_lwpins64()
29 void test_lwpval32(unsigned val2, unsigned val1) { in test_lwpval32() argument
32 __lwpval32(val2, val1, 0x01234); in test_lwpval32()
35 void test_lwpval64(unsigned long long val2, unsigned val1) { in test_lwpval64() argument
38 __lwpval64(val2, val1, 0xABCDEF); in test_lwpval64()

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